公开(公告)号：US20170062590A1

公开(公告)日：2017-03-02

申请号：US15073065

申请日：2016-03-17

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/3086 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/324 ,  H01L29/66795

Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first fin end and a second fin end and the second cut fin having a first fin end and a second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin.

Abstract translation: 制造半导体器件的方法包括：在衬底中图形化翅片; 执行第一蚀刻工艺以去除所述翅片的一部分以将所述翅片切割成第一切割翅片和第二切割翅片，所述第一切割翅片具有第一翅片端部和第二翅片端部，所述第二切割翅片具有第一翅片 端和第二鳍末端; 沿着第一翅片端部的端壁和第一切割翅片的第二翅片端部的端壁以及第一翅片端部的端壁和第二切割翅片的第二翅片端部的端壁形成氧化物层; 将衬垫设置在设置在第一切割翅片的第一翅片端部的端壁上的氧化物层上以形成双层衬垫; 以及执行第二蚀刻工艺以去除所述第二切割翅片的一部分。

公开(公告)号：US20170062233A1

公开(公告)日：2017-03-02

申请号：US14841951

申请日：2015-09-01

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/31 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/16 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/3086 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/324 ,  H01L29/66795

Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first fin end and a second fin end and the second cut fin having a first fin end and a second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin.

公开(公告)号：US20170040325A1

公开(公告)日：2017-02-09

申请号：US15168725

申请日：2016-05-31

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Rama Kambhampati ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

Abstract translation: 一种用于形成场效应晶体管的方法包括在第一鳍上形成第一虚拟栅极堆叠，在第二鳍片上形成第二虚拟栅极叠层，在第一伪栅极叠层上沉积第一层间隔物材料， 虚拟栅极堆叠和第二鳍片，在第一伪栅极堆叠和第一鳍片上构图第一掩模层，蚀刻以去除第一层间隔物材料的部分并形成邻近第二伪栅极叠层的间隔区， 第一掩模层，在所述第二鳍上外延生长硅材料，在所述第一隔离层材料层上沉积氧化物层，所述第一外延材料和所述第二伪栅极堆叠，以及在所述层上沉积第二隔离层材料层 的氧化物质。

公开(公告)号：US09564358B1

公开(公告)日：2017-02-07

申请号：US14849269

申请日：2015-09-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes forming a trench in a passivating layer between neighboring fins. A barrier is formed in the trench. Conductive contacts are formed in the passivating layer to provide electrical connectivity to the fins. The conductive contacts are in direct contact with sidewalls of the barrier. A semiconductor device includes a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier.

Abstract translation: 形成半导体器件的方法包括在相邻散热片之间的钝化层中形成沟槽。 在沟槽中形成屏障。 导电触点形成在钝化层中以提供与鳍片的电连接。 导电触头与屏障的侧壁直接接触。 半导体器件包括在一对鳍上的钝化层。 阻挡层延伸穿过钝化层并在一对翅片之间并且电隔离散热片。 电触头通过钝化层形成到散热片。 电触点直接接触屏障的侧壁。

公开(公告)号：US20170018463A1

公开(公告)日：2017-01-19

申请号：US14800970

申请日：2015-07-16

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  The Research Foundation for The State University of New York

Inventor： Huiming Bu ,  Hui-feng Li ,  Vijay Narayanan ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L21/76832 ,  H01L21/285 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0895 ,  H01L29/66795 ,  H01L29/7851

Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

Abstract translation: 晶体管器件包括衬底; 形成在所述基板上的源极区域和漏极区域; 以及与所述源极区域和所述漏极区域中的至少一个接触形成的源极/漏极接触部，所述源极/漏极接触部包括导电金属和设置在所述导电金属与所述源极和漏极区域中的至少一个之间的双层 包括与导电金属接触的金属氧化物层的双层以及与源区和漏区中的至少一个接触的二氧化硅层。

公开(公告)号：US09536981B1

公开(公告)日：2017-01-03

申请号：US14868414

申请日：2015-09-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Xiuyu Cai ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.

Abstract translation: 一种用于制造场效应晶体管器件的方法，包括在衬底上形成翅片，在鳍片上形成第一虚拟栅极堆叠和第二虚拟栅极堆叠，形成与鳍片相邻的间隔物，第一伪栅极堆叠和第二虚拟栅极 栅极堆叠，蚀刻以去除所述鳍片的部分并形成由所述间隔物部分地限定的第一空腔，在所述第一腔体中沉积绝缘体材料，在第一虚拟栅极堆叠和所述鳍片的部分上图案化掩模，蚀刻以去除暴露部分 并且在所述鳍的暴露部分上外延生长第一半导体材料。

公开(公告)号：US09525069B2

公开(公告)日：2016-12-20

申请号：US14576611

申请日：2014-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andres Bryant ,  Jeffrey B. Johnson ,  Effendi Leobandung ,  Tenko Yamashita

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.

Abstract translation: 一种制造FinFET器件的方法包括：形成具有覆盖掩埋氧化物（BOX）层的半导体层的绝缘体上硅（SOI）衬底; 蚀刻半导体层以在多个翅片结构和BOX层之间形成多个翅片结构和半导体层间隙; 在至少一个栅极区上沉积牺牲栅极，其中栅极区域分离源区和漏区; 在牺牲栅极的垂直侧壁上设置偏置间隔物; 去除牺牲门; 去除所述栅极区域中的半导体层间隙，以防止所述栅极区域中的所述多个翅片结构的合流; 以及制造覆盖栅极区域中的鳍结构的高k电介质金属栅极结构。

公开(公告)号：US09508597B1

公开(公告)日：2016-11-29

申请号：US14858154

申请日：2015-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zuoguang Liu ,  Xin Sun ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/06 ,  H01L29/49 ,  H01L27/088 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/0834 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/66356 ,  H01L29/7391

Abstract: A method for forming a tunneling field effect transistor includes forming gate structures over a semiconductor fin on a substrate having at least two pitches between the gate structures and recessing the fin between the gate structures. A first dielectric layer is deposited over the fin to fill in a first gap between the gate structures having a smaller pitch therebetween. A second gap between the gate structures having a larger pitch is filled with a second dielectric layer. The first gap is opened by etching the first dielectric layer while the second dielectric layer protects from opening the second gap. A source region is formed on the fin in the first gap. A dielectric fills the source region in the first gaps. The second gap is opened by etching the second dielectric layer and the first dielectric layer. A drain region is formed on the fin in the second gap.

Abstract translation: 形成隧道场效应晶体管的方法包括在半导体鳍片上形成栅极结构，该栅极结构在基板上形成，栅极结构之间具有至少两个间距，并且在栅极结构之间使翅片凹陷。 第一电介质层沉积在鳍片上以填充栅极结构之间的间距较小的第一间隙。 具有较大间距的栅极结构之间的第二间隙被第二介电层填充。 通过蚀刻第一介电层来打开第一间隙，而第二介电层保护不会打开第二间隙。 源区域形成在第一间隙中的翅片上。 电介质填充第一间隙中的源极区域。 通过蚀刻第二介电层和第一介电层来打开第二间隙。 漏极区域形成在第二间隙中的鳍片上。

公开(公告)号：US09478549B2

公开(公告)日：2016-10-25

申请号：US14529332

申请日：2014-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Tenko Yamashita

IPC: H01L21/84 ,  H01L27/108 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L27/10826 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211

Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.

公开(公告)号：US20160126352A1

公开(公告)日：2016-05-05

申请号：US14994549

申请日：2016-01-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/84 ,  H01L29/08 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847

Abstract: A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed.

Abstract translation: 提供了包括手柄基板，下绝缘体层，埋入半导体层，上绝缘体层和顶部半导体层的基板。 半导体鳍片可以通过在去除鳍片区域中的上绝缘体层和顶部半导体层之后图案化掩埋半导体层的一部分而形成，而平面器件区域被蚀刻掩模保护。 在翅片区域形成一次性填充材料部分，并且可以在平面装置区域中形成浅沟槽隔离结构。 去除一次性填充材料部分，并且可以同时形成用于平面场效应晶体管和鳍式场效应晶体管的栅极叠层。 或者，可以形成一次性栅极结构和平坦化介电层，并且随后可以形成替换栅极堆叠。