公开(公告)号：US10026810B2

公开(公告)日：2018-07-17

申请号：US15475917

申请日：2017-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Guillorn ,  Isaac Lauer ,  Nicolas J. Loubet

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/3213

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first nanosheet stack in a first device region with layers of a first channel material and layers of a sacrificial material. A second nanosheet stack is formed in a second device region with layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away, but the liner protects the second channel material from the etch. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices in the first and second device regions.

公开(公告)号：US09997613B2

公开(公告)日：2018-06-12

申请号：US15431987

申请日：2017-02-14

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/0223 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78696

Abstract: A semiconductor device includes a plurality of gate stacks spaced apart from each other on a substrate, an etch stop layer formed on an upper surface of each gate stack, a dielectric cap layer formed on each etch stop layer, a plurality of source/drain regions formed on the substrate between respective pairs of adjacent gate stacks, and a plurality of contacts respectively corresponding to each source/drain region, wherein the contacts are separated from the gate structures and contact their corresponding source/drain regions.

公开(公告)号：US20180040730A1

公开(公告)日：2018-02-08

申请号：US15606937

申请日：2017-05-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Isaac Lauer ,  Jiaxing Liu ,  Renee T. Mo

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/10

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02428 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/845 ,  H01L29/1033 ,  H01L29/66568 ,  H01L29/66818

Abstract: A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

公开(公告)号：US09887264B2

公开(公告)日：2018-02-06

申请号：US15245851

申请日：2016-08-24

Applicant: International Business Machines Corporation

Inventor： Jack O. Chu ,  Szu Lin Cheng ,  Isaac Lauer ,  Kuen-Ting Shiu ,  Jeng-Bang Yau

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/762 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor structure includes a plurality of semiconductor fins located on a semiconductor substrate, in which each of the semiconductor fins comprises a sequential stack of a buffered layer including a III-V semiconductor material and a channel layer including a III-V semiconductor material. The semiconductor structure further includes a gap filler material surrounding the semiconductor fins and including a plurality of trenches therein. The released portions of the channel layers of the semiconductor fins located in the trenches constitute nanowire channels of the semiconductor structure, and opposing end portions of the channel layers of the semiconductor fins located outside of the trenches constitute a source region and a drain region of the semiconductor structure, respectively. In addition, the semiconductor structure further includes a plurality of gates structures located within the trenches that surround the nanowire channels in a gate all around configuration.

公开(公告)号：US09812370B2

公开(公告)日：2017-11-07

申请号：US15332207

申请日：2016-10-24

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/336 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/24 ,  H01L29/10 ,  H01L29/45 ,  H01L29/735 ,  H01L27/06 ,  H01L21/84

CPC classification number: H01L21/8249 ,  H01L21/244 ,  H01L21/84 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/735

Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

公开(公告)号：US09812321B2

公开(公告)日：2017-11-07

申请号：US15254442

申请日：2016-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L21/0228 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

公开(公告)号：US20170294357A1

公开(公告)日：2017-10-12

申请号：US15626734

申请日：2017-06-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Guillorn ,  Isaac Lauer ,  Nicolas J. Loubet

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first stack in a first device region, the first stack including layers of a first channel material and layers of a sacrificial material. A second stack is formed in a second device region, the second stack including layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away using a wet etch that is selective to the sacrificial material and the second channel material and does not affect the first channel material or the liner. The liner protects the second channel material from the wet etch.

公开(公告)号：US09748404B1

公开(公告)日：2017-08-29

申请号：US15055830

申请日：2016-02-29

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/78696 ,  H01L21/02236 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/78654

Abstract: A method for fabricating a semiconductor device comprises forming a sacrificial layer of a first semiconductor material on a substrate, a layer of a second semiconductor material on the sacrificial layer, and a layer of a third semiconductor material on the layer of the second semiconductor material. Portions of the layer of the deposited material are removed to form a first nanowire arranged on the sacrificial fin and a second nanowire arranged on the first nanowire. An oxidizing process is performed that forms a first layer of oxide material on exposed portions of the second nanowire and a second layer of oxide material on exposed portions of the sacrificial fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness.

公开(公告)号：US09653547B1

公开(公告)日：2017-05-16

申请号：US15072461

申请日：2016-03-17

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/768 ,  H01L27/088 ,  H01L29/10

CPC classification number: H01L29/66545 ,  H01L21/0223 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78696

Abstract: A semiconductor device includes a plurality of gate stacks spaced apart from each other on a substrate, an etch stop layer formed on an upper surface of each gate stack, a dielectric cap layer formed on each etch stop layer, a plurality of source/drain regions formed on the substrate between respective pairs of adjacent gate stacks, and a plurality of contacts respectively corresponding to each source/drain region, wherein the contacts are separated from the gate structures and contact their corresponding source/drain regions.

公开(公告)号：US09647139B2

公开(公告)日：2017-05-09

申请号：US14846428

申请日：2015-09-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/786 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/0228 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.