公开(公告)号：US20160307777A1

公开(公告)日：2016-10-20

申请号：US15092973

申请日：2016-04-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Ryota HODO ,  Yuta IIDA ,  Satoru OKAMOTO

IPC: H01L21/4757 ,  H01L21/473 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/02063 ,  H01L21/76814 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/7869 ,  H01L2221/1063

Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.

Abstract translation: 提供一分钟晶体管。 提供具有低寄生电容的晶体管。 提供具有高频特性的晶体管。 提供包括晶体管的电极。 提供了一种新颖的电极。 电极包括含有金属的第一导电层，绝缘层和第二导电层。 绝缘层形成在第一导电层上。 在绝缘层上形成掩模层。 使用掩模层作为掩模的等离子体蚀刻绝缘层，由此在绝缘层中形成开口以到达第一导电层。 在氧气氛中至少对开口进行等离子体处理。 通过等离子体处理，在开口中的第一导电层上形成含金属的氧化物。 除去氧化物，然后在开口中形成第二导电层。

公开(公告)号：US20160126360A1

公开(公告)日：2016-05-05

申请号：US14992570

申请日：2016-01-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78606 ,  H01L27/1156 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.

公开(公告)号：US20150372122A1

公开(公告)日：2015-12-24

申请号：US14739127

申请日：2015-06-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota HODO ,  Motomu KURATA ,  Shinya SASAGAWA

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/4757 ,  H01L29/49 ,  H01L21/441 ,  H01L29/24 ,  H01L29/45

CPC classification number: H01L29/66969 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/441 ,  H01L21/465 ,  H01L21/467 ,  H01L21/47573 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

Abstract: To provide a semiconductor device which occupies a small area and is highly integrated. A first conductive layer is formed; a first insulating layer is formed over the first conductive layer; a second conductive layer is formed over the first insulating layer using the same material as the first conductive layer; a third conductive layer is formed over the second conductive layer; a second insulating layer is formed over the third conductive layer; a resist mask is formed over the second insulating layer; etching is successively performed from the upper layer and an opening is formed in the first conductive layer and the diameter of the opening in the second conductive layer is increased in the same step; and a contact hole where an upper surface of the first conductive layer is exposed is formed by etching the first insulating layer.

Abstract translation: 提供一种半导体器件，占用小面积并高度集成。 形成第一导电层; 在所述第一导电层上形成第一绝缘层; 使用与第一导电层相同的材料在第一绝缘层上形成第二导电层; 在所述第二导电层上形成第三导电层; 在所述第三导电层上形成第二绝缘层; 在第二绝缘层上形成抗蚀剂掩模; 从上层依次进行蚀刻，并且在第一导电层中形成开口，并且在相同步骤中增加第二导电层中的开口的直径; 并且通过蚀刻第一绝缘层来形成暴露第一导电层的上表面的接触孔。

公开(公告)号：US20150093855A1

公开(公告)日：2015-04-02

申请号：US14567235

申请日：2014-12-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Akihiro ISHIZUKA ,  Shinya SASAGAWA

IPC: H01L21/4757 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/47573 ,  H01L21/02554 ,  H01L21/02587 ,  H01L21/02639 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a miniaturized semiconductor device with stable electric characteristics in which a short-channel effect is suppressed. Further, to provide a manufacturing method of the semiconductor device. The semiconductor device (transistor) including a trench formed in an oxide insulating layer, an oxide semiconductor film formed along the trench, a source electrode and a drain electrode which are in contact with the oxide semiconductor film, a gate insulating layer over the oxide semiconductor film, a gate electrode over the gate insulating layer is provided. The lower corner portions of the trench are curved, and the side portions of the trench have side surfaces substantially perpendicular to the top surface of the oxide insulating layer. Further, the width between the upper ends of the trench is greater than or equal to 1 time and less than or equal to 1.5 times the width between the side surfaces of the trench.

Abstract translation: 提供具有稳定电特性的小型化半导体器件，其中抑制短沟道效应。 此外，提供半导体器件的制造方法。 包括形成在氧化物绝缘层中的沟槽，沿着沟槽形成的氧化物半导体膜，与氧化物半导体膜接触的源电极和漏电极的半导体器件（晶体管），氧化物半导体上的栅极绝缘层 提供了栅极绝缘层上的栅电极。 沟槽的下角部分是弯曲的，并且沟槽的侧部具有大致垂直于氧化物绝缘层的顶表面的侧表面。 此外，沟槽的上端之间的宽度大于或等于沟槽的侧表面之间的宽度的1倍且小于或等于1.5倍。

公开(公告)号：US20150084049A1

公开(公告)日：2015-03-26

申请号：US14558989

申请日：2014-12-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akihiro ISHIZUKA ,  Yutaka YONEMITSU ,  Shinya SASAGAWA

IPC: H01L23/535 ,  H01L29/786

CPC classification number: H01L23/535 ,  H01L21/31111 ,  H01L27/1225 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor and having improved electric characteristics. The semiconductor device includes an oxide semiconductor film, a gate electrode overlapping the oxide semiconductor film, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The method includes the steps of forming a first insulating film including gallium oxide over and in contact with the oxide semiconductor film; forming a second insulating film over and in contact with the first insulating film; forming a resist mask over the second insulating film; forming a contact hole by performing dry etching on the first insulating film and the second insulating film; removing the resist mask by ashing using oxygen plasma; and forming a wiring electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode through the contact hole.

Abstract translation: 本发明的目的是提供一种制造包括氧化物半导体并具有改善的电特性的半导体器件的方法。 半导体器件包括氧化物半导体膜，与氧化物半导体膜重叠的栅电极，以及与氧化物半导体膜电连接的源电极和漏电极。 该方法包括以下步骤：在氧化物半导体膜上形成包含氧化镓并与其接触的第一绝缘膜; 在所述第一绝缘膜上形成第二绝缘膜并与所述第一绝缘膜接触; 在所述第二绝缘膜上形成抗蚀剂掩模; 通过对所述第一绝缘膜和所述第二绝缘膜进行干蚀刻来形成接触孔; 使用氧等离子体通过灰化去除抗蚀剂掩模; 以及通过所述接触孔形成电连接到所述栅电极，所述源电极和所述漏电极中的至少一个的布线。

公开(公告)号：US20150079730A1

公开(公告)日：2015-03-19

申请号：US14548955

申请日：2014-11-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC: H01L21/465 ,  H01L29/66

CPC classification number: H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

Abstract translation: 本发明的目的是建立一种其中使用氧化物半导体的半导体器件的制造中的加工技术。 在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成氧化物半导体层，通过湿蚀刻加工氧化物半导体层，形成岛状氧化物半导体层 形成导电层以覆盖岛状氧化物半导体层，通过干蚀刻处理导电层以形成源电极，并且通过干蚀刻除去漏电极和岛状氧化物半导体层的一部分， 在岛状氧化物半导体层中形成凹部。

公开(公告)号：US20140332801A1

公开(公告)日：2014-11-13

申请号：US14337583

申请日：2014-07-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L27/1156 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/78606 ,  H01L29/78636 ,  H01L29/78696

Abstract: A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof was devised. In addition, the portions of the source electrode and the drain electrode which are proximate to the channel formation region are formed in a later step than the other portions thereof, whereby a bottom-gate transistor with a short channel length can be manufactured.

Abstract translation: 提供具有短沟道长度的底栅晶体管和制造晶体管的方法。 设计了具有短沟道长度的底栅晶体管，其中靠近沟道形成区的源电极和漏电极的部分比其它部分薄。 此外，靠近沟道形成区域的源电极和漏极的部分以比其它部分稍后的步骤形成，由此可以制造具有短沟道长度的底栅晶体管。

公开(公告)号：US20140291674A1

公开(公告)日：2014-10-02

申请号：US14227459

申请日：2014-03-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Hiroaki HONDA ,  Takashi HAMADA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02334 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78696

Abstract: A substrate having an insulating surface is prepared; a stacked film including a first oxide semiconductor layer and a second oxide semiconductor layer is formed over the substrate; a mask layer is formed over part of the stacked film and then dry etching treatment is performed, so that the stacked film is removed, with a region provided with the mask layer remaining, and a reaction product is formed on a side surface of the remaining stacked film; the reaction product is removed by wet etching treatment after removal of the mask layer; a source electrode and a drain electrode are formed over the stacked film; and a third oxide semiconductor layer, a gate insulating film, and a gate electrode are stacked and formed in this order over the stacked film, and the source electrode and the drain electrode.

Abstract translation: 准备具有绝缘表面的基板; 在基板上形成包括第一氧化物半导体层和第二氧化物半导体层的层叠膜; 在层叠膜的一部分上形成掩模层，然后进行干法蚀刻处理，从而除去保留有掩模层的区域，在其余的侧面形成反应产物 叠片 去除掩模层后，通过湿蚀刻处理去除反应产物; 源极电极和漏电极形成在堆叠膜上; 并且第三氧化物半导体层，栅极绝缘膜和栅极电极按顺序层叠并形成在堆叠膜上，以及源电极和漏电极。

公开(公告)号：US20140273343A1

公开(公告)日：2014-09-18

申请号：US14287494

申请日：2014-05-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunichi ITO ,  Miyuki HOSOBA ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC: H01L29/66

CPC classification number: H01L29/66969 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/7869

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by dry etching in which an etching gas is used, and a second etching step is performed by wet etching in which an etchant is used.

Abstract translation: 目的是以低成本，高生产率制造包括氧化物半导体的半导体器件，使得通过减少曝光掩模的数量来简化光刻工艺。 在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜 光透过该掩模以具有多个强度。 在蚀刻步骤中，通过使用蚀刻气体的干蚀刻进行第一蚀刻步骤，并且通过使用蚀刻剂的湿蚀刻进行第二蚀刻步骤。

公开(公告)号：US20140252351A1

公开(公告)日：2014-09-11

申请号：US14284733

申请日：2014-05-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo ISOBE ,  Yutaka OKAZAKI ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/10879 ,  H01L27/1104 ,  H01L27/11521 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.

Abstract translation: 在栅极绝缘膜上形成与氧化物半导体膜重叠的第一导电膜，通过使用经受电子束曝光的抗蚀剂选择性蚀刻第一导电膜形成栅电极，在栅绝缘膜上形成第一绝缘膜 和栅电极，在栅电极未被露出的同时去除第一绝缘膜的一部分，在第一绝缘膜，抗反射膜，第一绝缘膜和栅极绝缘膜上形成防反射膜 使用经受电子束曝光的抗蚀剂选择性蚀刻，以及与氧化物半导体膜的一端接触的源极和与氧化物半导体膜的另一端接触的第一绝缘膜和漏电极的一端，以及 形成第一绝缘膜的另一端。