公开(公告)号：US20200144106A1

公开(公告)日：2020-05-07

申请号：US16177854

申请日：2018-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LiCausi ,  Chanro Park ,  Ruilong Xie ,  Andre P. Labonte

IPC: H01L21/768

Abstract: An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.

公开(公告)号：US10410933B2

公开(公告)日：2019-09-10

申请号：US15602225

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Hui Zang ,  Guowei Xu

IPC: H01L21/3213 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02

Abstract: This disclosure relates to a method of replacement metal gate patterning for nanosheet devices including: forming a first and a second nanosheet stack on a substrate, the first and the second nanosheet stacks being adjacent to each other and each including vertically adjacent nanosheets separated by a distance; depositing a first metal surrounding the first nanosheet stack and a second portion of the first metal surrounding the second nanosheet stack; forming an isolation region between the first nanosheet stack and the second nanosheet stack; removing the second portion of the first metal surrounding the second nanosheet stack with an etching process, the isolation region preventing the etching process from reaching the first portion of the first metal and thereby preventing removal of the first portion of the first metal; and depositing a second metal surrounding each of the nanosheets of the second nanosheet stack.

公开(公告)号：US10283617B1

公开(公告)日：2019-05-07

申请号：US15800563

申请日：2017-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Dong-Ick Lee ,  Min Gyu Sung ,  Chanro Park

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L21/321 ,  H01L29/417 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/08 ,  H01L21/3105

Abstract: Device structures and fabrication methods for a field-effect transistor. A first dielectric spacer adjacent to a sidewall of a gate placeholder structure. A contact placeholder structure is formed adjacent to the first dielectric spacer such that the first dielectric spacer is arranged laterally between the gate placeholder structure and the contact placeholder structure. The contact placeholder structure and the first dielectric spacer are recessed to open a space over the contact placeholder structure and the first dielectric spacer. A second dielectric spacer is formed in the space adjacent to the sidewall of the gate placeholder structure and over the first dielectric spacer.

公开(公告)号：US10217846B1

公开(公告)日：2019-02-26

申请号：US15873156

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Min Gyu Sung ,  Chanro Park ,  Steven Soss ,  Hui Zang ,  Xusheng Wu ,  Yi Qi ,  Ajey P. Jacob ,  Murat K. Akarvardar ,  Siva P. Adusumilli ,  Jiehui Shu ,  Haigou Huang ,  John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L29/16 ,  H01L29/78

Abstract: Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.

公开(公告)号：US10217839B2

公开(公告)日：2019-02-26

申请号：US15468170

申请日：2017-03-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Kisup Chung ,  Victor Chan ,  Koji Watanabe

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/28

Abstract: Disclosed is a field effect transistor (FET) with a replacement metal gate (RMG) and a method of forming the FET. The RMG includes a conformal gate dielectric layer and a stack of gate conductor layers on the gate dielectric layer. The stack includes a conformal work function metal (WFM) layer and a conductive fill material (CFM) layer on the WFM layer. Within the stack, the top surface of the CFM layer is above the level of the top of an adjacent vertical portion of the WFM layer. A dielectric gate cap has a center portion and an edge portion. The center portion is above the top surface of the CFM layer and the edge portion is above the top of the adjacent vertical portion of the WFM layer and is further positioned laterally immediately adjacent to an upper portion of an outer sidewall of the CFM layer.

公开(公告)号：US20190051563A1

公开(公告)日：2019-02-14

申请号：US15676005

申请日：2017-08-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process.

公开(公告)号：US20190013241A1

公开(公告)日：2019-01-10

申请号：US15641927

申请日：2017-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Lars Liebmann ,  Daniel Chane ,  Chanro Park ,  Nigel Cave ,  Vimal Kamineni

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.

公开(公告)号：US10103238B1

公开(公告)日：2018-10-16

申请号：US15652890

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Tek Po Rinus Lee ,  Haigou Huang ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L21/311 ,  H01L29/786 ,  H01L21/02

Abstract: Methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a plurality of nanosheet channel layers and a plurality of first sacrificial layers that are alternatingly arranged with the nanosheet channel layers. The body feature is located on a second sacrificial layer. The first sacrificial layers are recessed relative to the nanosheet channel layers to form a plurality of first cavities indented into a sidewall of the body feature. A plurality of dielectric spacers are formed that fill the first cavities. After forming the dielectric spacers, the second sacrificial layer is removed with an etching process to define a second cavity that extends completely beneath the body feature. A dielectric layer is formed in the second cavity.

公开(公告)号：US10090402B1

公开(公告)日：2018-10-02

申请号：US15658835

申请日：2017-07-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Chang Ho Maeng ,  Pei Liu ,  Junsic Hong ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/06

Abstract: The method includes steps for improving gate cut isolation region critical dimension (CD) control. Prior to replacement metal gate (RMG) formation, a first sacrificial gate adjacent to first and second channel regions and made of a first sacrificial material (e.g., polysilicon or amorphous silicon) is replaced with a second sacrificial gate made of a second sacrificial material (e.g., amorphous carbon) that is more selectively and anisotropically etchable. A cut is made, dividing the second sacrificial gate into first and second sections, and the cut is then filled with a dielectric to form the gate cut isolation region. The second sacrificial material ensures that, when an opening in a mask pattern used to form the cut extends over a gate sidewall spacer and interlayer dielectric (ILD) material, recesses are not form within the spacer or ILD. Thus, the CD of the isolation region can be controlled.

公开(公告)号：US10014389B2

公开(公告)日：2018-07-03

申请号：US15219403

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/3086 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

Abstract: One illustrative method disclosed herein includes, among other things, forming channel semiconductor material for a nano-sheet device and a transistor device, forming a device gate insulation layer on both the nano-sheet device and on the transistor device, and forming first and second sacrificial gate structures for the nano-sheet device and the transistor device. In this example, the method also includes removing the sacrificial gate structures so as to define, respectively, first and second gate cavities, wherein the device gate insulation layer is exposed within each of the gate cavities, removing the device gate insulation layer for the transistor device from within the first gate cavity while leaving the device gate insulation layer in position within the second gate cavity, and forming first and second replacement gate structures in the first and second gate cavities, respectively.