公开(公告)号：US20110227207A1

公开(公告)日：2011-09-22

申请号：US12819111

申请日：2010-06-18

Applicant: Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

Inventor： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

IPC: H01L23/52 ,  H01L23/495 ,  H01L21/00

CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/81 ,  H01L24/84 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

Abstract: The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

Abstract translation: 本发明涉及具有插入金属夹结构的半导体管芯堆叠的引线框架。 水平投影从夹子结构延伸，以确保夹子结构在制造过程中保持水平。

公开(公告)号：US20110221008A1

公开(公告)日：2011-09-15

申请号：US12722528

申请日：2010-03-12

Applicant: Jun Lu ,  Kai Liu ,  Yan Xun Xue

Inventor： Jun Lu ,  Kai Liu ,  Yan Xun Xue

IPC: H01L23/52 ,  H01L27/088 ,  H01L21/70 ,  H01L23/28

CPC classification number: H01L21/565 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L25/07 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.

Abstract translation: 具有用于内部连接的连接板的半导体封装包括：多个芯片，每个芯片在顶表面上具有多个接触区域; 一个或多个连接板具有多个电隔离的连接板部分，每个连接板部分连接半导体芯片的接触区域。 制造半导体封装的方法包括将一个或多个连接板连接到多个半导体芯片的步骤，施加模制材料以封装芯片和连接板，将连接板的多个连接板部分分开浅 切割或磨削。

公开(公告)号：US20110193208A1

公开(公告)日：2011-08-11

申请号：US13092059

申请日：2011-04-21

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L24/49 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/13099 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/32506 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73153 ,  H01L2224/73255 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

Abstract translation: 本发明涉及倒装芯片的半导体封装以及制造半导体封装的方法。 半导体芯片包括金属氧化物半导体场效应晶体管。 在包括第一基底，第二基底和第三基底的裸片上，在第一基底和第二基底的顶表面上进行半蚀刻或冲孔，以获得多个凹槽，该凹槽将第一基底 进入包括多个第一连接区域的多个区域，并且将第二基座的顶表面分成包括至少第二连接区域的多个区域。 半导体芯片在第一连接区域和第二连接区域处连接到管芯焊盘。

公开(公告)号：US20110129961A1

公开(公告)日：2011-06-02

申请号：US12592596

申请日：2009-11-30

Applicant: Yan Xun Xue ,  Jun Lu

Inventor： Yan Xun Xue ,  Jun Lu

IPC: H01L21/78

CPC classification number: H01L23/49551 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: This invention discloses a process for packaging semiconductor device with external leads. The process includes comprises Step 1: providing a lead frame comprising a plurality of lead frame units connected by a plurality of metal beams, each lead frame unit comprising a die pad and a plurality of leads located on opposite sides of the die pad; adhering a semiconductor chip onto each of the die pad, and providing a plurality of metal connections for electrically connecting each chip to its corresponding leads; Step 2 providing a plastic molding material to enclose the plurality of the lead frame units, the metal beams, the chips, and at least portions of the metal connections; Step 3 removing a portion of the plastic molding material above the metal beams to expose the metal beams and portions of the leads in connection with the metal beams; and Step 4 separating each lead frame unit, forming a plurality of individual semiconductor plastic package components with external leads.

Abstract translation: 本发明公开了一种用外部引线封装半导体器件的方法。 该方法包括步骤1：提供引线框架，该引线框架包括由多个金属梁连接的多个引线框架单元，每个引线框架单元包括管芯焊盘和位于管芯焊盘的相对侧上的多个引线; 将半导体芯片粘附到每个芯片焊盘上，并且提供多个金属连接件，用于将每个芯片电连接到其相应的引线; 步骤2提供塑料模制材料以封闭多个引线框架单元，金属梁，芯片以及金属连接件的至少部分; 步骤3，移除金属梁上方的塑料成型材料的一部分，以暴露金属梁和引线的与金属梁相关的部分; 以及步骤4分离每个引线框架单元，用外部引线形成多个单独的半导体塑料封装部件。

公开(公告)号：US20110107589A1

公开(公告)日：2011-05-12

申请号：US13007551

申请日：2011-01-14

Applicant: Francois Hebert ,  Tao Feng ,  Jun Lu

Inventor： Francois Hebert ,  Tao Feng ,  Jun Lu

IPC: H01F7/06

CPC classification number: H01F17/0033 ,  H01F1/344 ,  H01F41/046 ,  H01F2017/002 ,  Y10T29/4902

Abstract: An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.

Abstract translation: 电感器可以包括平面铁氧体磁芯。 第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。 在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。 第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。 第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。 每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。 导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

公开(公告)号：US20110101511A1

公开(公告)日：2011-05-05

申请号：US12608853

申请日：2009-10-29

Applicant: Jun Lu ,  François Hébert

Inventor： Jun Lu ,  François Hébert

IPC: H01L23/52 ,  H01L21/98 ,  H01L23/495

CPC classification number: H01L23/492 ,  H01L24/36 ,  H01L24/40 ,  H01L25/071 ,  H01L25/072 ,  H01L25/16 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/37099

Abstract: The present invention features a power semiconductor package and a method of forming the same that includes forming, in the body, a stress relief region disposed between a pair of mounting regions and attaching a semiconductor die in each of the mounting regions. The semiconductor die has first and second sets of electrical contacts with the first set being on a first surface of the semiconductor die and the second set being disposed upon a second surface of the semiconductor die opposite to the first surface. The first set is in electrical communication with the mounting region. Walls are formed on outer sides of the pair of mounting regions, defining a shaped body, with the shaped body and walls defining an electrically conductive path that extends from the first set and terminates on side of the package common with the second set.

Abstract translation: 本发明的特征在于功率半导体封装及其形成方法，其包括在主体中形成设置在一对安装区域之间的应力释放区域，并且在每个安装区域中安装半导体管芯。 半导体管芯具有第一组和第二组电触点，第一组在半导体管芯的第一表面上，第二组设置在与第一表面相对的半导体管芯的第二表面上。 第一组与安装区域电连通。 壁形成在一对安装区域的外侧，限定成形体，成形体和壁限定从第一组延伸并终止于与第二组共同的包装侧的导电路径。

公开(公告)号：US20110095409A1

公开(公告)日：2011-04-28

申请号：US12606290

申请日：2009-10-27

Applicant: Yan Xun Xue ,  Jun Lu ,  Le Shi ,  Liang Zhao

Inventor： Yan Xun Xue ,  Jun Lu ,  Le Shi ,  Liang Zhao

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L24/73 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/371 ,  H01L2224/37599 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.

Abstract translation: 公开了一种将引线框封装内的互连板连接到半导体管芯的方法。 基座引线框架设置有用于附接半导体管芯的管芯焊盘。 提供互连板，用于附接到基底引线框架和半导体管芯。 将基准注册功能添加到基准引线框架和板对准特征到互连板上，其中配准特征被设计成彼此匹配，使得在互连板到基底引线框架的接近时，两个配准特征将相互接合并引导彼此引起伴随 互连板与基座引线框架的自对准连接。 接下来，使互连板靠近基底引线框架以将板对准特征接合并锁定到基准对准特征，从而完成互连板连接到半导体管芯并形成引线框封装。

公开(公告)号：US20110093672A1

公开(公告)日：2011-04-21

申请号：US12970536

申请日：2010-12-16

Applicant: Parag Gokhale ,  Jun Lu ,  Yanhui Lu ,  Yu Wang ,  Rajiv Kottomtharayil

Inventor： Parag Gokhale ,  Jun Lu ,  Yanhui Lu ,  Yu Wang ,  Rajiv Kottomtharayil

IPC: G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0604 ,  G06F3/0605 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0665 ,  G06F3/0683 ,  G06F3/0686 ,  G06F11/1453 ,  G06F12/00 ,  G06F12/02 ,  G06F2201/815 ,  H04L41/046 ,  H04L41/22 ,  H04L67/1097

Abstract: In one embodiment of the invention, a method is provided for retrieving certain electronic information previously stored on certain storage media after a threshold set in the storage retention criteria has been exceeded in an electronic information storage system that stores electronic information on storage media in accordance with a storage retention criteria is provided. The method includes storing a record in a memory associated with a system manager that assigns the storage retention criteria to the certain electronic data, designating the storage media available for overwrite after the threshold set in the storage retention policy has been exceeded, identifying the certain storage media available for overwrite, and retrieving information from the certain media after the threshold set in the storage retention policy has been exceeded.

Abstract translation: 在本发明的一个实施例中，提供了一种方法，用于在根据存储媒体存储电子信息的电子信息存储系统中超过存储保留标准中设定的阈值之后，检索先前存储在某些存储介质上的某些电子信息 提供存储保留标准。 所述方法包括将记录存储在与系统管理器相关联的存储器中，所述存储器将存储保留标准分配给所述某些电子数据，在已经超过所述存储保留策略中设置的阈值之后指定可用于覆盖的存储介质，识别所述特定存储 媒体可用于覆盖，并且在超出了存储保留策略中设置的阈值之后从某些媒体中检索信息。

公开(公告)号：US07882093B2

公开(公告)日：2011-02-01

申请号：US12794437

申请日：2010-06-04

Applicant: Rajiv Kottomtharayil ,  Parag Gokhale ,  Jun Lu

Inventor： Rajiv Kottomtharayil ,  Parag Gokhale ,  Jun Lu

IPC: G06F17/30

CPC classification number: G06F17/30094 ,  G06F11/1448 ,  G06F11/1453 ,  Y10S707/99934 ,  Y10S707/99955

Abstract: A method in a computer system for retrieving data from one of multiple copies of the data is provided, referred to as the data management system. The data management system receives a request identifying at least one data object to be accessed. Then, the data management system queries a metabase to locate data copies that contain the identified at least one data object, wherein the data copies are created from similar source data, and wherein for each data copy the metabase contains an indication of the availability of the copy relative to other copies. Next, the data management system determines one of the located data copies to use to access the identified at least one data object, wherein the determination is made based on the indicated availability contained in the metabase for each of the located data copies. Then, the data management system accesses the identified at least one data object using the determined one of the located data copies.

公开(公告)号：US07867605B2

公开(公告)日：2011-01-11

申请号：US10991565

申请日：2004-11-18

Applicant: James R Moran ,  Jun Lu

Inventor： James R Moran ,  Jun Lu

IPC: B32B17/06 ,  B32B17/10 ,  B32B27/08 ,  B32B27/30 ,  B32B27/36

CPC classification number: B32B27/36 ,  B32B17/10 ,  B32B17/10036 ,  B32B17/10743 ,  B32B17/10761 ,  Y10S428/91 ,  Y10T428/24942 ,  Y10T428/2495 ,  Y10T428/24967 ,  Y10T428/26 ,  Y10T428/266 ,  Y10T428/269 ,  Y10T428/31616 ,  Y10T428/3163 ,  Y10T428/31786 ,  Y10T428/31797 ,  B32B2367/00

Abstract: Composite laminate interlayers for adhering a glass laminate comprising two sheets of polyethylene terephthalate (PET) between layers of plasticized polyvinyl butyral (PVB) adhesive layers, wherein the two PET layers provide increased stiffness for the laminate without sacrificing the optical clarity of the laminate.

Abstract translation: 用于将包含两片聚对苯二甲酸乙二醇酯（PET）的玻璃层压板粘附在增塑聚乙烯醇缩丁醛（PVB）粘合剂层之间的复合层压夹层，其中两层PET层在层压板的光学透明度不牺牲的情况下提供增加的刚度。