公开(公告)号：US20240268091A1

公开(公告)日：2024-08-08

申请号：US18432870

申请日：2024-02-05

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Pankaj Sharma ,  Manuj Nahar ,  Nicholas R. Tapias ,  Scott E. Sills

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first conductive region; a second conductive region; a memory cell between the first and second conductive regions and including a first transistor including a first region coupled to the first and second conductive regions, and a charge storage structure separated from the first conduction region, and a second transistor including a second region coupled to the charge storage structure and the second conductive region; and a structure separated from the first region, the charge storage structure, and the second region by a dielectric structure, the structure forming part of a gate of the first transistor and the second transistor, and the structure including a first portion adjacent the dielectric structure, and a second portion adjacent the first portion, wherein the first portion includes a semiconductor material and the second portion includes a conductive material.

公开(公告)号：US20240206152A1

公开(公告)日：2024-06-20

申请号：US18542299

申请日：2023-12-15

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Scott E. Sills ,  Si-Woo Lee

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H10B12/31 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B12/482

Abstract: Systems, methods and apparatus are provided for a hybrid gate dielectric access device for vertical three-dimensional (3D) memory. The memory cell has a first horizontally oriented access device having a first source/drain region and a second source/drain region separated by a first channel region. The first access device is operatively controlled by a first gate. A hybrid gate dielectric separates the gate from the channel region and a horizontally oriented storage node coupled to the second source/drain region of the access device.

公开(公告)号：US20240188302A1

公开(公告)日：2024-06-06

申请号：US18520002

申请日：2023-11-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B51/20 ,  H10B41/10 ,  H10B41/20 ,  H10B51/10

CPC classification number: H10B51/20 ,  H10B41/10 ,  H10B41/20 ,  H10B51/10

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive structure; a ferroelectric portion encircling the conductive structure; a charge storage structure encircling the ferroelectric portion; a dielectric portion encircling the charge storage structure; a semiconductor portion encircling the dielectric portion; a first additional conductive structure adjacent a first side of the semiconductor portion; and a second additional conductive structure adjacent a second side of the semiconductor portion, wherein a direction from the first additional conductive structure to the second additional conductive structure is perpendicular to a direction of a length of the conductive structure.

公开(公告)号：US20240172432A1

公开(公告)日：2024-05-23

申请号：US18428325

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Yunfei Gao ,  Sanh D. Tang ,  Deepak Chandra Pandey

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240113223A1

公开(公告)日：2024-04-04

申请号：US18530113

申请日：2023-12-05

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Kirk D. Prall ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L29/786 ,  G11C11/409 ,  H01L29/423 ,  H01L29/66 ,  H10B12/00

CPC classification number: H01L29/78642 ,  G11C11/409 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/7869 ,  H10B12/05 ,  H10B12/30 ,  H10B12/50

Abstract: A transistor comprising threshold voltage control gates. The transistor also comprises active control gates adjacent opposing first sides of a channel region, the threshold voltage control gates adjacent opposing second sides of the channel region, and a dielectric region between the threshold voltage control gates and the channel region and between the active control gates and the channel region. A semiconductor device comprising memory cells comprising the transistor is also disclosed, as are systems comprising the memory cells, methods of forming the semiconductor device, and methods of operating a semiconductor device.

公开(公告)号：US20240099026A1

公开(公告)日：2024-03-21

申请号：US18519964

申请日：2023-11-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B63/00 ,  G11C5/12 ,  G11C13/00 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  G11C5/12 ,  G11C13/0002 ,  H01L21/823487 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696 ,  H10B63/22 ,  H10B63/24 ,  H10B63/34 ,  H10N70/011 ,  H10N70/245 ,  H10N70/828 ,  H10N70/841 ,  H10N70/883 ,  G11C11/401 ,  G11C2213/79

Abstract: Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material and the channel material includes a second, different material.

公开(公告)号：US20240074211A1

公开(公告)日：2024-02-29

申请号：US18238291

申请日：2023-08-25

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B63/00 ,  G11C5/06 ,  H10B63/10 ,  H10N70/00

CPC classification number: H10B63/34 ,  G11C5/063 ,  H10B63/10 ,  H10B63/845 ,  H10N70/883

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a conductive region; a memory cell including a memory element, a first portion, a second portion, a dielectric portion, and a third portion; and a data line formed over the second and third portions of the memory cell. The memory element is formed over the conductive region. The first portion is formed over the memory element and includes a first conductive material. The second portion is formed over the first portion and includes a second conductive material. The dielectric portion includes a first side adjacent the memory element, the first portion, and the second portion. The third portion includes a third conductive material and is adjacent a second side of the dielectric portion and separated from the memory element, the first portion, and the second portion by the dielectric portion.

公开(公告)号：US20240074138A1

公开(公告)日：2024-02-29

申请号：US18238269

申请日：2023-08-25

Applicant: Micron Technology, Inc.

Inventor： Durai Vishak Nirmal Ramaswamy ,  Karthik Sarpatwari ,  Kamal M. Karda ,  Pankaj Sharma

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line; a second data line adjacent the first data line and separated from the first data line by a first dielectric structure; and a memory cell formed over the first and second data lines. The memory cell includes a first transistor including a first channel region formed over and coupled to the first data line, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over and coupled to the second data line, wherein the charge storage structure is formed over and coupled to the second channel region; and a second dielectric structure between the first channel region and each of the second channel region and the charge storage structure.

公开(公告)号：US11856799B2

公开(公告)日：2023-12-26

申请号：US17182953

申请日：2021-02-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L21/8234 ,  H10B63/00 ,  G11C13/00 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  G11C5/12 ,  H10N70/00 ,  H10N70/20 ,  G11C11/401 ,  G11C11/16 ,  G11C11/22

CPC classification number: H10B63/84 ,  G11C5/12 ,  G11C13/0002 ,  H01L21/823487 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/7869 ,  H01L29/78642 ,  H01L29/78696 ,  H10B63/22 ,  H10B63/24 ,  H10B63/34 ,  H10N70/011 ,  H10N70/245 ,  H10N70/828 ,  H10N70/841 ,  H10N70/883 ,  G11C11/1659 ,  G11C11/2259 ,  G11C11/401 ,  G11C13/003 ,  G11C2213/79 ,  H01L29/78618

Abstract: Methods of forming a semiconductor device are disclosed. A method comprising forming a hybrid transistor supported by a substrate. Forming the hybrid transistor comprises forming a source including a first low bandgap high mobility material, and forming a channel including a high bandgap low mobility material coupled with the first low bandgap high mobility material. Forming the hybrid transistor further comprises forming a drain including a second low bandgap high mobility material coupled with the a high bandgap low mobility material, and forming a gate separated from the channel via a gate oxide material. Methods of forming a transistor are also disclosed.

公开(公告)号：US11805653B2

公开(公告)日：2023-10-31

申请号：US17145131

申请日：2021-01-08

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/11573 ,  H10B43/40 ,  G11C16/08 ,  H01L23/532 ,  H01L21/28 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H10B43/40 ,  G11C16/08 ,  H01L23/5329 ,  H01L29/40117 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.