公开(公告)号：US20170213836A1

公开(公告)日：2017-07-27

申请号：US15482610

申请日：2017-04-07

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L27/108 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/10879 ,  B82Y10/00 ,  H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/0814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/66909 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/1233 ,  H01L2029/7858

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

公开(公告)号：US20160293589A1

公开(公告)日：2016-10-06

申请号：US15175738

申请日：2016-06-07

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC: H01L27/01 ,  H01L23/525

CPC classification number: H01L27/016 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5252 ,  H01L23/5256 ,  H01L28/20 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

Abstract translation: 半导体处理步骤的顺序允许在公共结构内形成垂直和水平的纳米级蛇形电阻器和平行板电容器。 该方法利用CMP工艺不均匀性，其中绝缘材料的CMP抛光速率根据某些底层的形貌而变化。 通过在绝缘材料层之下建立这样的形貌，可以通过利用差分抛光速率在不同的区域产生绝缘体的不同膜厚度，从而避免使用光刻掩模。 在一个实施例中，使用仅需要两个掩模层的工艺，可以在公共介电块内形成多个电阻器和电容器作为紧凑的集成结构。 这样形成为一组集成电路元件的电阻器和电容器分别适合用作微电子熔丝和反熔丝，以保护下面的微电子电路。

公开(公告)号：US09437453B2

公开(公告)日：2016-09-06

申请号：US14231533

申请日：2014-03-31

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/302 ,  H01L21/321 ,  H01L21/67 ,  B24B37/005 ,  H01L21/02 ,  H01L21/66

CPC classification number: H01L21/3212 ,  B24B37/005 ,  H01L21/02074 ,  H01L21/6704 ,  H01L21/67207 ,  H01L21/67219 ,  H01L21/67253 ,  H01L21/67706 ,  H01L22/14 ,  H01L22/20

Abstract: CMP selectivity, removal rate, and uniformity are controlled both locally and globally by altering electric charge at the wafer surface. Surface charge characterization is performed by an on-board metrology module. Based on a charge profile map, the wafer can be treated in an immersion bath to impart a more positive or negative charge overall, or to neutralize the entire wafer before the CMP operation is performed. If charge hot spots are detected on the wafer, a charge pencil can be used to neutralize localized areas. One type of charge pencil bears a tapered porous polymer tip that is placed in close proximity to the wafer surface. Films present on the wafer absorb ions from, or surrender ions to, the charge pencil tip, by electrostatic forces. The charge pencil can be incorporated into a CMP system to provide an in-situ treatment prior to the planarization step or the slurry removal step.

Abstract translation: 通过改变晶片表面的电荷，局部和全局地控制CMP选择性，去除速率和均匀性。 表面电荷表征由机载测量模块执行。 基于电荷分布图，晶片可以在浸没浴中进行处理以赋予整体更多的正电荷或负电荷，或者在执行CMP操作之前中和整个晶片。 如果在晶片上检测到充电热点，则可以使用充电笔来中和局部区域。 一种类型的充电笔带有一个倾斜的多孔聚合物顶端，其被放置在紧靠晶片表面的位置。 存在于晶片上的膜通过静电力吸收离子或将离子放置到电荷铅笔尖。 电荷铅笔可以结合到CMP系统中以在平坦化步骤或浆料去除步骤之前提供原位处理。

公开(公告)号：US20160247722A1

公开(公告)日：2016-08-25

申请号：US15143969

申请日：2016-05-02

Applicant: International Business Machines Corporation ,  STMICROELECTRONICS, INC.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Akil K. Sutton ,  Terry Allen Spooner ,  Nicole A. Saulnier

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

公开(公告)号：US09425213B1

公开(公告)日：2016-08-23

申请号：US14788341

申请日：2015-06-30

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L27/12 ,  H01L27/02 ,  H01L21/84 ,  H01L21/266 ,  H01L21/265 ,  H01L21/308 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3081 ,  H01L27/0207 ,  H01L27/1211 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4236 ,  H01L29/66795

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

Abstract translation: 公开了一种模拟集成电路，其中短沟道晶体管堆叠在由绝缘层垂直分隔的长沟道晶体管的顶部。 通过这样的设计，可以生产高密度，高功率和高性能的模拟集成电路芯片，其包括彼此间隔足够远的短路和长通道设备，以避免串扰。 在一个实施例中，晶体管是FinFET，并且长沟道器件是多栅极FinFET。 在一个实施例中，将单镶嵌和双镶嵌装置组合在多层集成电路单元中。 小区可以包含短路和长通道设备的各种组合和配置。 可以通过简单地收缩细胞的尺寸并复制与原始细胞相同尺寸足迹的两个或更多个细胞来制造高密度细胞。

公开(公告)号：US09245955B2

公开(公告)日：2016-01-26

申请号：US13931509

申请日：2013-06-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Pietro Montanini

IPC: H01L29/165 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/66636 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress to the channel region of the NMOS transistors and compressive stress to the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

Abstract translation: 集成电路管芯包括硅衬底。 在硅衬底上形成PMOS和NMOS晶体管。 通过向NMOS晶体管的沟道区域引入拉伸应力和对PMOS晶体管的沟道区域的压缩应力来增加PMOS和NMOS晶体管的载流子迁移率。 通过在NMOS晶体管的沟道区域的下方包含SiGe区域来引入拉伸应力。 通过在PMOS晶体管的源极和漏极区域中包括SiGe的区域来引入压缩应力。

公开(公告)号：US09240375B2

公开(公告)日：2016-01-19

申请号：US13931692

申请日：2013-06-28

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC: H03H11/40 ,  H01L23/525 ,  H01F17/02 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5256 ,  H01F17/0006 ,  H01F17/02 ,  H01F2017/0073 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/5252 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

Abstract translation: 公开了纳米级电子元件，反熔丝和平面线圈电感器。 铜镶嵌工艺可用于制造所有这些电路元件。 可以使用低温铜蚀刻工艺来制造efuse和efuse样电感器。 电路元件可以通过以不同的配置和尺寸连接金属柱的矩阵来以模块化方式设计和构造。 金属柱的数量，或包括在电路元件中的电介质网的尺寸确定其电特性。 或者，电极和电感器可以由沉积在电介质柱的基体中的间隙金属形成，或者在蚀刻金属块中的柱状开口之后留下。 金属列的阵列还具有第二功能，作为可以改善抛光均匀性以代替常规虚拟结构的特征。 使用这种模块化阵列为集成电路设计人员提供了灵活性。

公开(公告)号：US20150001583A1

公开(公告)日：2015-01-01

申请号：US13931509

申请日：2013-06-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Pietro Montanini

IPC: H01L29/165 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/66636 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress to the channel region of the NMOS transistors and compressive stress to the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

Abstract translation: 集成电路管芯包括硅衬底。 在硅衬底上形成PMOS和NMOS晶体管。 通过向NMOS晶体管的沟道区域引入拉伸应力和对PMOS晶体管的沟道区域的压缩应力来增加PMOS和NMOS晶体管的载流子迁移率。 通过在NMOS晶体管的沟道区域的下方包含SiGe区域来引入拉伸应力。 通过在PMOS晶体管的源极和漏极区域中包括SiGe的区域来引入压缩应力。

公开(公告)号：US20140097539A1

公开(公告)日：2014-04-10

申请号：US13928084

申请日：2013-06-26

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Wei-Tsu Tseng ,  Tien-Jen Cheng ,  Laertis Economikos

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L23/522 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Pitch-dependent dishing and erosion following CMP treatment of copper features is quantitatively assessed by atomic force microscopy (AFM) and transmission electron microscopy (TEM). A new sequence of processing steps presented herein is used to prevent dishing and to reduce significantly the local pitch- and pattern density-induced CMP non-uniformity for copper metal lines having widths and spacing in the range of about 32-128 nm. The new process includes a partial copper deposition step followed by deposition of a silicon carbide/nitride (SiCxNy) blocking layer. A multi-step CMP process planarizes areas of the resulting irregular surface that have narrow features, while the blocking layer protects areas that have wide features.

Abstract translation: 通过原子力显微镜（AFM）和透射电子显微镜（TEM）定量评估CMP特征的CMP处理后的间距依赖性凹陷和侵蚀。 本文提出的新的处理步骤序列用于防止凹陷并显着减少具有宽度和间隔在约32-128nm范围内的铜金属线的局部间距和图案密度诱导的CMP不均匀性。 该新方法包括部分铜沉积步骤，然后沉积碳化硅/氮化物（SiC x N y）阻挡层。 多步CMP工艺平坦化具有窄特征的所得不规则表面的区域，而阻挡层保护具有广泛特征的区域。

公开(公告)号：US20140027933A1

公开(公告)日：2014-01-30

申请号：US14038574

申请日：2013-09-26

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Walter Kleemeier ,  Paul Ferreira ,  Ronald K. Sampson

IPC: H01L23/544 ,  H01L21/66

CPC classification number: H01L23/544 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract translation: 提供了一种装置，其包括具有第一对准结构的第一管芯，所述第一对准结构包括布置成图案的多个第一传输柱和位于所述第一管芯上的第二管芯，所述第二管芯具有第二对准结构，所述第二对准结构包括多个第二 传输列以与第一传输列相同的图案排列。 第一和第二透射柱分别与第一和第二模具的第一表面和第二表面共面。