公开(公告)号：US09515180B2

公开(公告)日：2016-12-06

申请号：US14588318

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Chun-chen Yeh ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28

CPC classification number: H01L29/7855 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28141 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7831 ,  H01L29/785

Abstract: A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions.

Abstract translation: 垂直狭缝晶体管包括半导体衬底中的凸起的源极，漏极和沟道区。 两个栅极位于半导体衬底的相应侧壁附近。 电介质材料将栅电极与源区和漏区分开。

公开(公告)号：US09502505B2

公开(公告)日：2016-11-22

申请号：US14587849

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing Liu ,  Thomas Skotnicki

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

Abstract translation: 集成电路管芯包括具有第一半导体材料层的衬底，第一半导体材料层上的介电材料层，以及介电材料层上的第二层半导体材料。 晶体管的扩展沟道区域位于第二半导体材料层中，与第二半导体材料层的顶表面，侧表面和潜在部分相互作用。 栅电介质位于第二层半导体材料的顶表面和暴露的侧表面上。 栅电极位于第二半导体材料层的顶表面和暴露的侧表面上。

公开(公告)号：US20160329253A1

公开(公告)日：2016-11-10

申请号：US14705291

申请日：2015-05-06

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Pierre Morin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02694 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

Abstract translation: 图案化拉伸应变硅层以在第一基板区域中形成第一组翅片，在第二基底区域中形成第二组翅片。 第二组翅片被拉伸应变材料覆盖，并且进行退火以使第二组翅片中的拉伸应变硅半导体材料松弛，并在第二区域中产生松弛的硅半导体翅片。 第一组翅片用掩模覆盖，硅 - 锗材料设置在松散的硅半导体鳍片上。 然后将来自硅锗材料的锗驱动到松散的硅半导体鳍片中，以在第二衬底区域（从其形成p沟道finFET器件）中产生压缩应变硅 - 锗半导体鳍片。 去除掩模以在第一衬底区域（从其形成n沟道finFET器件）中露出拉伸应变硅半导体鳍片。

公开(公告)号：US20160307964A1

公开(公告)日：2016-10-20

申请号：US14960595

申请日：2015-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

Abstract translation: 在支撑衬底上形成电阻随机存取存储器（RRAM）结构，并且包括第一电极和第二电极。 第一电极由支撑衬底上的硅化物翅片和覆盖硅化物翅片的第一金属衬垫层制成。 具有可配置电阻性能的电介质材料层覆盖第一金属衬垫的至少一部分。 第二电极由覆盖电介质材料层的第二金属衬垫层和与第二金属衬垫层接触的金属填充物制成。 非易失性存储单元包括电连接在存取晶体管和位线之间的RRAM结构。

公开(公告)号：US09466722B2

公开(公告)日：2016-10-11

申请号：US14584639

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/02181 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract translation: 用于集成电路的大面积电接触具有非平面，倾斜的底部轮廓。 倾斜的底部轮廓提供更大的电接触面积，从而降低接触电阻，同时保持小的接触足迹。 倾斜的底部轮廓可以通过凹陷下面的层来形成，其中底部轮廓可以被制造成具有V形，U形，月牙形或其它轮廓形状，其在垂直方向上至少包括基本上倾斜的部分 。 在一个实施例中，下层是FinFET的外延翅片。 制造低电阻电接触的方法采用用作硬掩模的薄蚀刻停止衬垫。 蚀刻停止衬垫，例如HfO 2，防止在形成接触期间相邻栅极结构的侵蚀。

公开(公告)号：US20160293638A1

公开(公告)日：2016-10-06

申请号：US15177715

申请日：2016-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Bruce Doris ,  Gauri Karve ,  Qing Liu

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L27/088 ,  H01L29/161 ,  H01L29/78 ,  H01L21/8258 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.

Abstract translation: 形成硅 - 锗材料的翅片并用外延生长的硅材料层覆盖。 然后形成虚拟晶体管栅极以在鳍的沟道上延伸。 侧壁间隔物形成在虚拟晶体管栅极的两侧，并直接在外延硅层的顶部。 外延生长的源极和漏极区域形成在邻近侧壁间隔物的虚拟晶体管栅极的每一侧上。 虚拟晶体管栅极和外延硅层的一部分（在所述虚设晶体管栅极之下）被去除并由金属栅极代替。

公开(公告)号：US20160293494A1

公开(公告)日：2016-10-06

申请号：US15180158

申请日：2016-06-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/84

CPC classification number: H01L21/823807 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78684

Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

公开(公告)号：US09461139B1

公开(公告)日：2016-10-04

申请号：US14722522

申请日：2015-05-27

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/10 ,  H01L21/02 ,  H01L29/735

CPC classification number: H01L29/735 ,  H01L21/28506 ,  H01L21/28518 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66257 ,  H01L29/7317

Abstract: A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in the semiconductor layer that is doped with a first conductivity type dopant at a first dopant concentration. The transistor emitter and collector are formed by regions doped with a second conductivity type dopant and located adjacent opposite sides of the base region. An extrinsic base includes an epitaxial semiconductor layer in contact with a top surface of the base region. The epitaxial semiconductor layer is doped with the first conductivity type dopant at a second dopant concentration greater than the first dopant concentration. Sidewall spacers on each side of the extrinsic base include an oxide liner on a side of the epitaxial semiconductor layer and the top surface of the base region.

Abstract translation: 双极晶体管由包括覆盖绝缘层的半导体层的衬底支撑。 晶体管基极由在第一掺杂浓度掺杂有第一导电型掺杂剂的半导体层中的基极区形成。 晶体管发射极和集电极由掺杂有第二导电型掺杂剂的区域形成，并且位于基极区域的相对侧。 外部基极包括与基极区域的顶表面接触的外延半导体层。 外延半导体层以大于第一掺杂剂浓度的第二掺杂剂浓度掺杂第一导电型掺杂剂。 外部基极的每一侧上的侧壁间隔物包括在外延半导体层的侧面上的氧化物衬垫和基极区域的顶表面。

公开(公告)号：US09431514B2

公开(公告)日：2016-08-30

申请号：US14577316

申请日：2014-12-19

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Bruce Doris ,  Gauri Karve

IPC: H01L21/335 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.

Abstract translation: 形成硅 - 锗材料的翅片并用外延生长的硅材料层覆盖。 然后形成虚拟晶体管栅极以在鳍的沟道上延伸。 侧壁间隔物形成在虚拟晶体管栅极的两侧，并直接在外延硅层的顶部。 外延生长的源极和漏极区域形成在邻近侧壁间隔物的虚拟晶体管栅极的每一侧上。 虚拟晶体管栅极和外延硅层的一部分（在所述虚设晶体管栅极之下）被去除并由金属栅极代替。

公开(公告)号：US09391200B2

公开(公告)日：2016-07-12

申请号：US14308045

申请日：2014-06-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L29/7848 ,  H01L21/30625 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Abstract translation: 描述了用于控制finFET鳍片的回蚀的技术和结构。 一个或多个层可以沉积在翅片上并被蚀刻。 可以使用平坦化层的蚀刻来确定邻近鳍片的一个或多个层的自限制蚀刻高度以及翅片的自限制蚀刻高度。 应变诱发材料可以形成在蚀刻翅片的区域，以引起finFET通道中的应变。