公开(公告)号：US20180053761A1

公开(公告)日：2018-02-22

申请号：US15242591

申请日：2016-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/308 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

公开(公告)号：US09899267B1

公开(公告)日：2018-02-20

申请号：US15390527

申请日：2016-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/8238 ,  H01L21/70 ,  H01L21/8234

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66795

Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, a plurality of gate electrodes, and a gate isolation structure. The semiconductor substrate includes a plurality of fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure.

公开(公告)号：US20180047848A1

公开(公告)日：2018-02-15

申请号：US15796874

申请日：2017-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Tang-Chun Weng ,  Chien-Hao Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.

公开(公告)号：US20180040693A1

公开(公告)日：2018-02-08

申请号：US15786611

申请日：2017-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chun-Yuan Wu

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76232 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.

公开(公告)号：US09875937B2

公开(公告)日：2018-01-23

申请号：US15356671

申请日：2016-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/322 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L21/324 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02667 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides a method for forming a semiconductor structure. Firstly, a substrate is provided, the substrate comprises an insulating layer and at least one first nano channel structure disposed thereon, a first region and a second region being defined on the substrate, next, a hard mask is formed within the first region, afterwards, an etching process is performed, to remove parts of the insulating layer within the second region, an epitaxial process is then performed, to form an epitaxial layer on the first nano channel structure, and an anneal process is performed, to transform the first nano channel structure and the epitaxial layer into a first nanowire structure, wherein the diameter of the first nanowire structure within the first region is different from the diameter of the first nanowire structure within the second region.

公开(公告)号：US09837540B2

公开(公告)日：2017-12-05

申请号：US14841628

申请日：2015-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Tang-Chun Weng ,  Chien-Hao Chen

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.

公开(公告)号：US09837417B1

公开(公告)日：2017-12-05

申请号：US15378050

申请日：2016-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/225 ,  H01L21/02 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/02129 ,  H01L21/0217 ,  H01L21/2256 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823892 ,  H01L27/0886 ,  H01L29/66803

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. The first sidewall spacer has a structure that is different from that of the second sidewall spacer.

公开(公告)号：US20170294539A1

公开(公告)日：2017-10-12

申请号：US15628658

申请日：2017-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02 ,  H01L29/08 ,  H01L29/24

CPC classification number: H01L29/7847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02667 ,  H01L21/26526 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

公开(公告)号：US20170263504A1

公开(公告)日：2017-09-14

申请号：US15604675

申请日：2017-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/3085 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

公开(公告)号：US09753373B2

公开(公告)日：2017-09-05

申请号：US14940108

申请日：2015-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Hung Wang

IPC: G03B27/42 ,  G03F7/20 ,  G01B11/27

CPC classification number: G03F7/70141 ,  G01B11/272 ,  G03F7/70633

Abstract: A semiconductor processing method is provided and includes the following steps. A first semiconductor process is performed for a wafer to obtain plural overlay datum (x, y), wherein x and y are respectively shift values in X-direction and Y-direction. Next, A re-correct process is performed by a computer, wherein the re-correct process comprises: (a) providing an overlay tolerance value (A, B) and an original out of specification value (OOS %), wherein A and B are respectively predetermined tolerance values in X-direction and Y-direction; (b) providing at least a k value (kx, ky); (c) modifying the overlay datum (x, y) according to the k value (kx, ky) to obtain at least a revised overlay datum (x′, y′); and (d) calculating a process parameter from the revised overlay datum (x′, y′). Lastly, a second semiconductor process is performed according to the process parameter . . . . The present invention further provides a lithography system.