中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

195 records (took 0.029 seconds)

    STT-MRAM cell structure incorporating piezoelectric stress material
    171.
    发明授权
    STT-MRAM cell structure incorporating piezoelectric stress material 有权
    STT-MRAM电池结构结合压电应力材料

    公开(公告)号：US09552858B2

    公开(公告)日：2017-01-24

    申请号：US14947978

    申请日：2015-11-20

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Steve Kramer ,  Gurtej Sandhu

    IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08

    CPC classification number: G11C11/161 ,  G11C11/16 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08

    Abstract: A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell.

    Abstract translation: 提供了包括压电材料的磁存储单元和操作存储单元的方法。 存储单元包括堆叠，并且压电材料可以形成为堆叠中的层或邻近电池堆的层。 压电材料可以用于在编程存储器单元期间引起瞬态应力以减小存储器单元的关键开关电流。

    Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same
    173.
    发明授权
    Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same 有权
    具有非磁性丝接触的存储单元及其操作和制造方法

    公开(公告)号：US09437809B2

    公开(公告)日：2016-09-06

    申请号：US14290477

    申请日：2014-05-29

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Gurtej Sandhu

    IPC: H01L43/08 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  H01F10/32 ,  H01L27/22 ,  H01F41/30

    CPC classification number: H01L43/08 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3268 ,  H01F10/329 ,  H01F41/306 ,  H01F41/307 ,  H01L27/228 ,  Y10S977/70

    Abstract: A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

    Abstract translation: 提供包括非磁性细丝接触的磁性单元结构以及制造该结构的方法。 磁性单元结构包括自由层，钉扎层，自由层和被钉扎层之间的绝缘层，以及绝缘层中的非磁性细丝接触，其电连接自由层和被钉扎层。 非磁性细丝接触由非磁性源层形成，也在自由层和被钉扎层之间。 灯丝接触引导编程电流通过磁性电池结构，使得自由层中编程电流的横截面面积小于结构的横截面。 自由层中编程电流的横截面积的减小使编程电流能够达到自由层中的关键开关电流密度并切换自由层的磁化，对磁性单元进行编程。

    Integrated Circuitry Comprising Nonvolatile Memory Cells And Methods Of Forming A Nonvolatile Memory Cell
    174.
    发明申请
    Integrated Circuitry Comprising Nonvolatile Memory Cells And Methods Of Forming A Nonvolatile Memory Cell 有权
    包含非易失性存储单元的集成电路和形成非易失性存储单元的方法

    公开(公告)号：US20160133835A1

    公开(公告)日：2016-05-12

    申请号：US14981198

    申请日：2015-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  John K. Zahurak

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1266 ,  H01L21/28114 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L27/2481 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66621 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1691

    Abstract: An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.

    Abstract translation: 集成电路具有包括第一电极，第二电极和离子导电材料的非易失性存储单元。 第一和第二电极中的至少一个具有直接接受离子导电材料接受的电化学活性表面。 第二电极位于第一电极的正上方。 第一电极在第一方向上横向延伸，并且离子导电材料沿与第一方向不同并与第一方向相交的第二方向延伸。 仅在第一和第二方向相交的情况下，第一电极直接接收在离子导电材料上。 公开了包括方法实施例的其它实施例。

    Memory Cells, Methods of Forming Memory Cells and Methods of Forming Memory Arrays
    175.
    发明申请
    Memory Cells, Methods of Forming Memory Cells and Methods of Forming Memory Arrays 有权
    记忆单元，形成记忆单元的方法和形成记忆阵列的方法

    公开(公告)号：US20160005962A1

    公开(公告)日：2016-01-07

    申请号：US14854212

    申请日：2015-09-15

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  John K. Zahurak

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

    Abstract: Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.

    Abstract translation: 一些实施例包括在一对电极之间具有多个可编程材料结构的存储器单元。 可编程材料结构之一具有第一边缘，另一个可编程材料结构具有接触第一边缘的第二边缘。 一些实施例包括形成存储器单元阵列的方法。 第一可编程材料段形成在底部电极上。 第一可编程材料段沿第一轴线延伸。 第二可编程材料的线形成在第一可编程材料段上，并且形成为沿与第一轴相交的第二轴线延伸。 第二可编程材料线具有接触第一可编程材料段的上表面的下表面。 顶部电极线形成在第二可编程材料线上。

    Bipolar switching memory cell with built-in “on” state rectifying current-voltage characteristics
    177.
    发明授权
    Bipolar switching memory cell with built-in “on” state rectifying current-voltage characteristics 有权
    具有内置“on”状态的双极开关存储单元整流电流电压特性

    公开(公告)号：US09224458B2

    公开(公告)日：2015-12-29

    申请号：US13930952

    申请日：2013-06-28

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Gurtej Sandhu

    IPC: H01L45/00 ,  G11C13/00

    CPC classification number: G11C13/0002 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149

    Abstract: A memory array is disclosed having bipolar current-voltage (IV) resistive random access memory cells with built-in “on” state rectifying IV characteristics. In one embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/semiconductor stack that forms a Schottky diode when switched to the “on” state. In another embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/tunnel barrier/electrode stack that forms a metal-insulator-metal device when switched to the “on” state. Methods of operating the memory array are also disclosed.

    Abstract translation: 公开了具有内置“on”状态整流IV特性的双极电流 - 电压（IV）电阻随机存取存储器单元的存储器阵列。 在一个实施例中，双极开关电阻随机存取存储器单元可以具有当切换到“导通”状态时形成肖特基二极管的金属/固体电解质/半导体堆叠。 在另一个实施例中，双极开关电阻随机存取存储器单元可以具有当切换到“导通”状态时形成金属 - 绝缘体 - 金属器件的金属/固体电解质/隧道势垒/电极堆叠。 还公开了操作存储器阵列的方法。

    Variable resistance memory with lattice array using enclosing transistors
    178.
    发明授权
    Variable resistance memory with lattice array using enclosing transistors 有权
    具有栅格阵列的可变电阻存储器使用封装晶体管

    公开(公告)号：US09209395B2

    公开(公告)日：2015-12-08

    申请号：US13776354

    申请日：2013-02-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jun Liu

    IPC: G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  H01L45/00 ,  G11C11/4097 ,  G11C13/00 ,  H01L27/24

    CPC classification number: G11C13/0069 ,  G11C5/06 ,  G11C5/063 ,  G11C11/4097 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

    Abstract: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

    Abstract translation: 可变电阻存储器阵列，编程可变电阻存储元件和形成阵列的方法。 可变电阻存储器阵列形成有围绕每个相变存储元件的多个字线晶体管。 为了对所选择的可变电阻存储元件进行编程，所有位线都以相同的电压接地或偏置。 选择与所选择的可变电阻存储元件接触的顶部电极选择线。 具有围绕所选择的可变电阻存储元件的字线晶体管的字线被接通以向该元件提供编程电流。 电流从所选择的顶部电极选择线通过可变电阻存储元件流入周围字线晶体管的公共源极/漏极区域，跨越晶体管到最近的位线触点。 字线被图案化成各种格子构型。

    Memory arrays and associated methods of manufacturing
    179.
    发明授权
    Memory arrays and associated methods of manufacturing 有权
    内存阵列和相关的制造方法

    公开(公告)号：US09209393B2

    公开(公告)日：2015-12-08

    申请号：US14136093

    申请日：2013-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: H01L45/00 ,  G11C13/00 ,  G11C5/06 ,  H01L27/24

    CPC classification number: H01L45/141 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0023 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/1691

    Abstract: Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first direction and a first contact line and a second contact line extending along a second direction different from the first direction. The first and second contact lines are generally parallel to each other. The memory array also includes a memory node that includes a first memory cell electrically connected between the access line and the first contact line to form a first circuit, and a second memory cell electrically connected between the access line and the second contact line to form a second circuit different from the first circuit.

    Abstract translation: 本文公开了存储器阵列和相关的制造方法。 在一个实施例中，存储器阵列包括沿着第一方向延伸的访问线和沿着不同于第一方向的第二方向延伸的第一接触线和第二接触线。 第一和第二接触线通常彼此平行。 存储器阵列还包括存储器节点，其包括电连接在接入线路和第一接触线路之间以形成第一电路的第一存储器单元，以及电连接在接入线路和第二接触线路之间的第二存储器单元， 第二电路不同于第一电路。

Patent Agency Ranking