Systems and methods for clock synchronization in a data acquisition system

    公开(公告)号:US10033390B2

    公开(公告)日:2018-07-24

    申请号:US14747068

    申请日:2015-06-23

    Abstract: A system may include a sampling circuit, a temperature calibration system, a phase detector, a virtual phase-locked loop, and a sample rate converter. The sampling circuit may be configured to generate a series of digitally-sampled data at a sampling frequency provided by a local clock. The temperature calibration system may be configured to determine a temperature-based timing compensation with respect to the local clock. The phase detector may be configured to estimate an error of the local clock in view of the reference clock. The virtual phase-locked loop may be configured to generate a virtual clock based on the temperature-based timing compensation and the error. The sample rate converter may be configured to generate a corrected series of digitally-sampled data in response to the virtual clock by interpolating the series of digitally-sampled data to correct for the error.

    Systems and methods for reduction of audio artifacts in an audio system with dynamic range enhancement

    公开(公告)号:US09998823B2

    公开(公告)日:2018-06-12

    申请号:US14507372

    申请日:2014-10-06

    Abstract: In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path.A signal path may have an analog path portion and a digital signal path portion. The digital portion may have a selectable digitally-controlled gain and may be configured to convert a digital audio input signal into an analog input signal in conformity with the selectable digitally-controlled gain, the digital signal path portion comprising a modulator including a forward path and a feedback path. The forward path may include a loop filter for generating a filtered signal responsive to the digital audio input signal and a feedback signal, a quantizer responsive to the filtered signal for generating a quantized signal, and a first gain element configured to apply the selectable digitally-controlled gain to a signal within the forward path. The feedback path may be configured to generate the feedback signal responsive to the quantized signal, the feedback path including a second gain element having a gain inversely proportional to the selectable digitally-controlled gain.

    Three phase power quality measurement using asynchronous, isolated single phase circuits

    公开(公告)号:US09766278B2

    公开(公告)日:2017-09-19

    申请号:US13739909

    申请日:2013-01-11

    CPC classification number: G01R25/00 G01R29/18

    Abstract: A system and method utilize multiple, asynchronous, voltage isolated integrated power data circuits (IPDCs) to respectively determine one or more power parameters of a multi-phase power distribution system. In at least one embodiment, the power parameters represent differences between voltage phases of a multi-phase power distribution system. In at least one embodiment, the IPDCs each sense a voltage or current from a single phase of a three-phase power distribution system. Additionally, the IPDCs are electrically isolated from each other and, thus, in at least one embodiment, can utilize voltage divider or shunt resistor sensing without being subject to high voltages representative of the difference between voltage phases. Additionally, in at least one embodiment, each of the IPDCs utilizes a separate clock signal to determine phase sequence and phase angle deltas of one or more three phase voltages of the three-phase power distribution system.

    Proportional feedback for reduced overshoot and undershoot in a switched output

    公开(公告)号:US09742399B2

    公开(公告)日:2017-08-22

    申请号:US14270319

    申请日:2014-05-05

    Inventor: Dan Shen

    Abstract: Embodiments of apparatuses and methods for proportional feedback for reduced overshoot and undershoot in a switched output are described. An embodiment of an apparatus includes a switching output stage configured to receive an input signal and provide a responsive output signal. The apparatus may also include a pulling circuit coupled to one of the first switching device and the second switching device. The pulling circuit may pull a control voltage of power transistors in the switching output stage to reduce impedance of at least one of the transistors in response to a determination that the output signal at the common output node is outside of a predetermined range of a threshold value. Pulling strength may increase as a voltage difference between the output signal and one of the first supply voltage and the second supply voltage increases.

Patent Agency Ranking