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    ENABLE/DISABLE OF MEMORY CHUNKS DURING MEMORY ACCESS
    183.
    发明申请
    ENABLE/DISABLE OF MEMORY CHUNKS DURING MEMORY ACCESS 有权
    内存访问期间启用/禁用存储器

    公开(公告)号：US20150262636A1

    公开(公告)日：2015-09-17

    申请号：US14725697

    申请日：2015-05-29

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa ,  Satoru Tamada ,  Koichi Kawai ,  Tetsuji Manabe

    IPC: G11C8/12 ,  G11C7/00

    CPC classification number: G11C8/12 ,  G11C7/00 ,  G11C7/18 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C2207/005 ,  G11C2207/2245

    Abstract: Apparatuses and methods involving accessing memory cells are described. In one such method, chunks of memory cells in a memory array are enabled to be accessed and then one or more of the chunks are disabled from being accessed. In one such apparatus, an array includes chunks of memory cells and a chunk selector circuit coupled to each chunk to enable the memory cells in the respective chunk to be accessed. Additional embodiments are described.

    Abstract translation: 描述了涉及访问存储器单元的装置和方法。 在一种这样的方法中，可以访问存储器阵列中的存储器单元块，然后禁止一个或多个块被访问。 在一种这样的装置中，阵列包括存储器单元的块和耦合到每个块的块选择器电路，以使得可以访问相应块中的存储器单元。 描述其他实施例。

    APPARATUSES INCLUDING MEMORY ARRAYS WITH SOURCE CONTACTS ADJACENT EDGES OF SOURCES
    184.
    发明申请
    APPARATUSES INCLUDING MEMORY ARRAYS WITH SOURCE CONTACTS ADJACENT EDGES OF SOURCES 有权
    包含源数据库的存储器阵列的设备

    公开(公告)号：US20150255478A1

    公开(公告)日：2015-09-10

    申请号：US14200348

    申请日：2014-03-07

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: H01L27/115

    CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/249

    Abstract: Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge.

    Abstract translation: 本文描述了包括三维（3D）存储器件和包括其的系统的各种装置。 在一个实施例中，3D存储器设备可以包括至少两个源; 至少两个存储器阵列分别形成并耦合到所述至少两个源; 以及源极导体，电源分别使用邻近所述源的一个或多个边缘的源极触点耦合到所述至少两个源。 所述至少两个存储器阵列中的每一个可以包括存储器单元，控制栅极和数据线。 在源的边缘和邻近边缘的源接触之间没有数据线。

    DEVICES FOR SHIELDING A SIGNAL LINE OVER AN ACTIVE REGION
    185.
    发明申请
    DEVICES FOR SHIELDING A SIGNAL LINE OVER AN ACTIVE REGION 有权
    用于屏蔽主动区域的信号线的装置

    公开(公告)号：US20150015319A1

    公开(公告)日：2015-01-15

    申请号：US14501796

    申请日：2014-09-30

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: H03K17/16

    CPC classification number: H03K17/162 ,  H01L23/5225 ,  H01L29/4238 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line.

    Abstract translation: 多路晶体管包括有源区，包括沟道区和杂质区。 栅极与沟道区电介分离。 信号线与杂质区介电分离。 导电屏蔽设置在信号线和沟道区之间并且与电介质分离。 在一些多路径晶体管中，沟道区包括在导电屏蔽之下的延伸沟道区，多路晶体管包括不同的导通路径，不同的导通路径中的至少一个在扩展通道区域中以基本独立的方式进行 信号线上的电压。 在其他多路径晶体管中，导电屏蔽可操作地耦合到杂质区，并且多路晶体管包括不同的导电路径，不同导电路径中的至少一个在导电屏蔽之下，基本上与 信号线。

    MEMORY DEVICES HAVING DATA LINES INCLUDED IN TOP AND BOTTOM CONDUCTIVE LINES
    186.
    发明申请
    MEMORY DEVICES HAVING DATA LINES INCLUDED IN TOP AND BOTTOM CONDUCTIVE LINES 有权
    具有包含在顶部和底部导电线中的数据线的存储器件

    公开(公告)号：US20140321188A1

    公开(公告)日：2014-10-30

    申请号：US14330737

    申请日：2014-07-14

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C5/06

    CPC classification number: G11C5/06 ,  G11C5/063 ,  G11C8/14 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Some embodiments include apparatuses and methods having a first set of conductive lines, a second set of conductive lines, and memory cells located in different levels of the apparatuses and arranged in memory cell strings. At least a portion of the first set of conductive lines is configured as a first set of data lines. At least a portion of the second set of conductive lines is configured as a second set of data lines. Each of the memory strings is coupled to a respective conductive line in the first set of conductive lines and a respective conductive line in the second set of conductive lines. Other embodiments including additional apparatuses and methods are described.

    Abstract translation: 一些实施例包括具有第一组导线的设备和方法，第二组导线，以及位于设备的不同级别并被布置在存储器单元串中的存储单元。 第一组导线的至少一部分被配置为第一组数据线。 第二组导线的至少一部分被配置为第二组数据线。 每个存储器串耦合到第一组导线中的相应导线和第二组导线中的相应导线。 描述包括附加装置和方法的其他实施例。

    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS
    188.
    发明申请
    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS 有权
    用于控制存储器操作中的身体潜力的装置和方法

    公开(公告)号：US20140160851A1

    公开(公告)日：2014-06-12

    申请号：US13707067

    申请日：2012-12-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

    IPC: G11C16/06

    CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

    Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

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