公开(公告)号：US20210265204A1

公开(公告)日：2021-08-26

申请号：US17094700

申请日：2020-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Po-Cheng Shih ,  Syun-Ming Jang ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/027 ,  G03F7/038 ,  G03F7/039 ,  G03F7/20

Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

公开(公告)号：US10916656B2

公开(公告)日：2021-02-09

申请号：US16937359

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Chang Sung ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li ,  Tsz-Mei Kwok

IPC: H01L29/78 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H01L27/088 ,  H01L21/02

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

公开(公告)号：US10861971B2

公开(公告)日：2020-12-08

申请号：US15589259

申请日：2017-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Chang Sung ,  Tsz-Mei Kwok ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/84 ,  H01L21/02 ,  H01L21/324 ,  H01L29/04 ,  H01L29/165

Abstract: The present disclosure relates to a transistor device having a strained source/drain region. In some embodiments, the transistor device has a gate structure arranged over a semiconductor substrate. The transistor device also has a strained source/drain region arranged within the semiconductor substrate along a side of the gate structure. The strained source/drain region includes a first layer and a second layer over the first layer. The first layer has a strain inducing component with a first concentration profile that decreases as a distance from the second layer decreases, and the second layer has the strain inducing component with a second non-zero concentration profile that is discontinuous with the first concentration profile.

公开(公告)号：US20200350433A1

公开(公告)日：2020-11-05

申请号：US16933622

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Han-Chi Lin ,  Chunyao Wang ,  Ching Yu Huang ,  Tze-Liang Lee ,  Yung-Chih Wang

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/3065 ,  H01L27/088 ,  H01L21/8234

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

公开(公告)号：US10519545B2

公开(公告)日：2019-12-31

申请号：US15169037

申请日：2016-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mo Lin ,  Yi-Hung Lin ,  Jr-Hung Li ,  Tze-Liang Lee ,  Ting-Gang Chen ,  Chung-Ting Ko

IPC: C23C16/455 ,  H01J37/32 ,  C23C16/509 ,  H01L21/02 ,  H01L21/285

Abstract: A system and method for plasma enhanced deposition processes. An exemplary semiconductor manufacturing system includes a susceptor configured to hold a semiconductor wafer and a sector disposed above the susceptor. The sector includes a first plate and an overlying second plate, operable to form a plasma there between. The first plate includes a plurality of holes extending through the first plate, which vary in at least one of diameter and density from a first region of the first plate to a second region of the first plate.

公开(公告)号：US10515822B2

公开(公告)日：2019-12-24

申请号：US15187027

申请日：2016-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hau Shiu ,  Chung-Chi Ko ,  Tze-Liang Lee ,  Yu-Yun Peng

IPC: H01L21/02 ,  H01L21/311 ,  G03F7/09 ,  H01L21/768

Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile film having a second tensile stress that is less than the first tensile stress or a compressive film. The first insulating film and second insulating film are formed of a same material. A metal hard mask layer is formed on the second insulating film.

公开(公告)号：US10325994B2

公开(公告)日：2019-06-18

申请号：US15959900

申请日：2018-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Tang Peng ,  Tai-Chun Huang ,  Teng-Chun Tsai ,  Cheng-Tung Lin ,  De-Fang Chen ,  Li-Ting Wang ,  Chien-Hsun Wang ,  Huan-Just Lin ,  Yung-Cheng Lu ,  Tze-Liang Lee

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L21/02 ,  H01L23/00 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/06 ,  H01L23/29 ,  H01L23/31 ,  H01L27/088

Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.

公开(公告)号：US20190006227A1

公开(公告)日：2019-01-03

申请号：US15725996

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Lin TSAI ,  Shing-Chyang Pan ,  Sung-En Lin ,  Tze-Liang Lee ,  Jung-Hau Shiu ,  Jen Hung Wang

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02019 ,  H01L21/0337 ,  H01L2221/101

Abstract: The present disclosure describes a method of forming a dielectric layer or a dielectric stack on a photoresist layer while minimizing or avoiding damage to the photoresist. In addition, the dielectric layer or dielectric stack can till high-aspect ratio openings and can be removed with etching. The dielectric layer or dielectric stack can be deposited with a conformal, low-temperature chemical vapor deposition process or a conformal, low-temperature atomic layer deposition process that utilizes a number of precursors and plasmas or reactant gases.

公开(公告)号：US10084040B2

公开(公告)日：2018-09-25

申请号：US15290772

申请日：2016-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Chun Huang ,  Bor Chiuan Hsieh ,  Pei-Ren Jeng ,  Tai-Chun Huang ,  Tze-Liang Lee

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/0649 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/324 ,  H01L21/76227 ,  H01L29/66795

Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

公开(公告)号：US09873943B2

公开(公告)日：2018-01-23

申请号：US15169999

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anthony Lin ,  Ching-Lun Lai ,  Pei-Ren Jeng ,  Tze-Liang Lee

IPC: C23C16/455 ,  C23C16/44 ,  H01L21/02 ,  C23C16/458

CPC classification number: C23C16/45551 ,  C23C16/4412 ,  C23C16/45519 ,  C23C16/45578 ,  C23C16/4584 ,  H01L21/0228

Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a processing chamber; a wafer stage configured in the processing chamber, the wafer stage is operable to secure and rotate a plurality of wafers around an axis; a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber; and a second chemical delivery mechanism configured in the processing chamber to provide a second chemical to a second reaction zone in the processing chamber. The second chemical delivery mechanism includes an edge chemical injector and a first radial chemical injector.