公开(公告)号：US09496361B1

公开(公告)日：2016-11-15

申请号：US14869987

申请日：2015-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/417 ,  H01L29/40 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L29/4958 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/76897 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545

Abstract: A manufacturing method of a semiconductor structure includes the following steps. Gate trenches are formed in a first dielectric layer on a semiconductor substrate. A sidewall spacer layer is formed on the semiconductor substrate and on at least two sides of each gate trench. A plurality of first metal gates is formed on the semiconductor substrate. Each of the first metal gates includes an upper part and a lower part connected to the upper part, the lower part is formed in one of the gate trenches, and the upper part covers at least a part of the sidewall spacer layer in a vertical direction. The upper part and the lower part of the first metal gate are formed by an identical process together.

Abstract translation: 半导体结构的制造方法包括以下步骤。 栅极沟槽形成在半导体衬底上的第一电介质层中。 在半导体衬底上和每个栅沟槽的至少两侧上形成侧壁间隔层。 多个第一金属栅极形成在半导体衬底上。 每个第一金属栅极包括连接到上部的上部和下部，下部形成在一个栅极沟槽中，并且上部在垂直方向上覆盖侧壁间隔层的至少一部分 。 第一金属栅极的上部和下部由相同的工艺一起形成。

公开(公告)号：US20160329248A1

公开(公告)日：2016-11-10

申请号：US15190209

申请日：2016-06-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/3085 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

Abstract translation: 半导体器件及其形成方法，所述半导体器件包括衬底，多个鳍状结构和绝缘层。 衬底具有鳍状场效应晶体管（finFET）区域，第一区域，第二区域和第三区域。 第一区域，第二区域和第三区域分别具有第一表面，第二表面和第三表面，其中第一表面相对高于第二表面，而第二表面相对高于第三表面。 鳍状结构设置在鳍状场效应晶体管区域的表面上。 绝缘层覆盖第一表面，第二表面和第三表面。

公开(公告)号：US09490217B1

公开(公告)日：2016-11-08

申请号：US14687912

申请日：2015-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Lin ,  En-Chiuan Liou ,  Chia-Hung Wang ,  Sho-Shen Lee

IPC: H01L23/544 ,  H01L21/68 ,  H01L29/78

CPC classification number: H01L29/785 ,  G03F7/70633 ,  G03F7/70683

Abstract: An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.

Abstract translation: 在本发明中提供了用于确定在衬底上方与两个连续层形成的两个单独产生的图案之间的对准的覆盖标记，其中衬底和覆盖标记都包括具有不同取向的周期性结构的至少两个图案区域，以及 覆盖标记的周期性结构与衬底的周期性结构正交地重叠。

公开(公告)号：US20160315007A1

公开(公告)日：2016-10-27

申请号：US15201511

申请日：2016-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Yu-Cheng Tung

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L21/76895 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/3085 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/00 ,  H01L29/66545 ,  H01L29/66553

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; removing part of the gate structure; forming a first mask layer on the first ILD layer and the gate structure; removing the first mask layer on the first ILD layer and part of the first mask layer on the gate structure for forming a first hard mask on the gate structure; forming a second mask layer on the first ILD layer, the first hard mask, and the gate structure; and planarizing the second mask layer to form a second hard mask on the gate structure, in which the top surfaces of the first hard mask, the second hard mask, and the first ILD layer are coplanar.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的第一层间电介质（ILD）层; 去除栅极结构的一部分; 在第一ILD层和栅极结构上形成第一掩模层; 去除栅极结构上的第一ILD层上的第一掩模层和栅极结构上的第一掩模层的一部分，以在栅极结构上形成第一硬掩模; 在第一ILD层，第一硬掩模和栅极结构上形成第二掩模层; 以及平坦化所述第二掩模层以在所述栅极结构上形成第二硬掩模，其中所述第一硬掩模，所述第二硬掩模和所述第一ILD层的顶表面是共面的。

公开(公告)号：US20160284587A1

公开(公告)日：2016-09-29

申请号：US14687932

申请日：2015-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/34 ,  H01L21/033 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/033 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/34

Abstract: A semiconductor process including the following step is provided. A sacrificial layer is formed in a substrate. The sacrificial layer and the substrate are etched to form a trench in the sacrificial layer and the substrate. A first isolation material fills the trench, thereby a first isolation structure being formed. The sacrificial layer is patterned to form a plurality of sacrificial patterns. A plurality of spacers are formed beside the sacrificial patterns respectively. The sacrificial patterns are removed. Layouts of the spacers are transferred into the substrate, so that a plurality of fin structures are formed in the substrate. The spacers are then removed. The present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract translation: 提供包括以下步骤的半导体工艺。 在衬底中形成牺牲层。 蚀刻牺牲层和衬底以在牺牲层和衬底中形成沟槽。 第一隔离材料填充沟槽，从而形成第一隔离结构。 将牺牲层图案化以形成多个牺牲图案。 在牺牲图案旁边分别形成多个间隔物。 牺牲图案被去除。 间隔物的布置被转移到基底中，使得在基底中形成多个翅片结构。 然后移除间隔物。 本发明还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US20160276458A1

公开(公告)日：2016-09-22

申请号：US15170904

申请日：2016-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/768 ,  H01L29/24 ,  H01L29/267 ,  H01L21/285 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/6681 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823431 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2029/7858

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate, and a sacrificial mandrel is formed on the substrate, in which the sacrificial mandrel includes a first side and a second side with the indentation. Next, a spacer is formed adjacent to the first side and the second side of the sacrificial mandrel, the sacrificial mandrel is removed, and the spacer is used to remove part of the substrate for forming a fin-shaped structure and a dummy fin-shaped structure.

Abstract translation: 公开了半导体器件的制造方法。 首先，在基板上形成基板和牺牲芯棒，其中牺牲芯棒包括第一侧和具有凹陷的第二侧。 接下来，在牺牲心轴的第一侧和第二侧附近形成间隔件，去除牺牲心轴，并且使用间隔件去除用于形成翅片状结构的基板的一部分和虚拟翅片形状 结构体。

公开(公告)号：US09378973B1

公开(公告)日：2016-06-28

申请号：US14842845

申请日：2015-09-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L21/308 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L21/823412 ,  H01L29/66795

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of mandrels on the first region and a plurality of patterns on the second region, in which the widths of the patterns on the second region are greater than the widths of the mandrels on the first region; forming a hard mask on the second region to cover the patterns; and forming a cap layer on the first region and the second region to cover the mandrels and the hard mask.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有第一区域和第二区域的衬底; 在所述第一区域上形成多个心轴以及所述第二区域上的多个图案，其中所述第二区域上的图案的宽度大于所述第一区域上的所述心轴的宽度; 在所述第二区域上形成硬掩模以覆盖所述图案; 以及在所述第一区域和所述第二区域上形成盖层以覆盖所述心轴和所述硬掩模。

公开(公告)号：US20160104786A1

公开(公告)日：2016-04-14

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/092 ,  H01L21/28 ,  H01L21/321 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US20160018728A1

公开(公告)日：2016-01-21

申请号：US14335949

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Teng-Chin Kuo ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G03F1/38 ,  H01L21/027 ,  G03F7/20

CPC classification number: G03F1/38 ,  G03F7/20 ,  H01L21/0274

Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract translation: 本发明提供一种用于在半导体衬底上制造结构的光掩模，其包括光掩模衬底，第一图案，第二图案和禁止图案。 第一有源区，第二有源区被限定在光掩模基板上，除了第一有源区和第二有源区之外的区域被定义为禁止区。 第一图案设置在第一有源区中并对应于半导体衬底上的第一结构。 第二图案设置在第二有源区域中，并且对应于半导体衬底上的第二结构。 禁止图案设置在禁止区域中，其中禁止图案具有超过光刻分辨能力的尺寸，并且不用于在半导体基板上形成任何相应的结构。 本发明还提供一种制造半导体结构的方法。

公开(公告)号：US20150362905A1

公开(公告)日：2015-12-17

申请号：US14457136

申请日：2014-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Teng-Chin Kuo ,  Chia-Hung Wang ,  Tuan-Yen Yu ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G05B19/18 ,  G03F7/20

CPC classification number: G03F7/70633 ,  G03F1/42 ,  G03F7/70491 ,  G05B19/188 ,  G05B2219/45027 ,  G05B2219/45031

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract translation: 校正重叠错误的方法包括以下步骤。 首先，捕获设置在基板上的覆盖标记，以生成重叠标记信息。 覆盖标记包括至少一对第一标记图案和至少第一标记图案上方的第二标记图案。 然后，计算叠加标记信息以产生两个第一标记图案之间的偏移值，并产生第二标记图案与第一标记图案之一之间的偏移值。 最后，偏移值用于补偿偏移值，以产生修正的移位值。