公开(公告)号：US20180323155A1

公开(公告)日：2018-11-08

申请号：US16015091

申请日：2018-06-21

申请人： Alpha and Omega Semiconductor (Cayman) Ltd.

发明人： Xiaobin Wang ,  Madhur Bobde ,  Paul Thorup

IPC分类号： H01L23/00 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06

摘要： A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. A semiconductor substrate of a first conductivity type is provided. A plurality of first trenches arranged side by side in a first stripe layout extending along a first direction in a first preset area of the semiconductor substrate are formed. A plurality of second trenches arranged side by side in a second stripe layout extending along a second direction perpendicular to the first direction in a second preset area of the semiconductor substrate are formed. The plurality of first trenches and the plurality of second trenches are filled with a conductive material so as to form a plurality of control gates.

公开(公告)号：US10062685B2

公开(公告)日：2018-08-28

申请号：US15623210

申请日：2017-06-14

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Sik Lui ,  Ji Pan

IPC分类号： H02M1/34 ,  H01L27/06 ,  H01L29/8605 ,  H01L29/66 ,  H01L29/40 ,  H01L49/02 ,  H01L29/94 ,  H01L29/78

CPC分类号： H01L27/0629 ,  H01L28/20 ,  H01L29/407 ,  H01L29/66181 ,  H01L29/66666 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8605 ,  H01L29/94 ,  H02M1/34 ,  H02M2001/348

摘要： Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.

公开(公告)号：US10043736B2

公开(公告)日：2018-08-07

申请号：US15203803

申请日：2016-07-07

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Peter Wilson ,  Yan Huo ,  Zhiqiang Niu ,  Ming-Chen Lu

IPC分类号： H01L23/495 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L21/78 ,  H01L23/544 ,  H01L23/31 ,  H01L21/56

摘要： A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.

公开(公告)号：US10020389B2

公开(公告)日：2018-07-10

申请号：US15365931

申请日：2016-11-30

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Anup Bhalla ,  Tinggang Zhu

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/20 ,  H01L29/788 ,  H01L29/10 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/7786 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/408 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7785 ,  H01L29/7787 ,  H01L29/785 ,  H01L29/788

摘要： A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero-junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.

公开(公告)号：US10014381B2

公开(公告)日：2018-07-03

申请号：US14987759

申请日：2016-01-05

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  John Chen ,  Daniel Ng ,  Wenjun Li

IPC分类号： H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/861 ,  H01L29/872 ,  H01L29/06 ,  H01L27/02 ,  H01L29/10 ,  H01L29/49

CPC分类号： H01L29/4236 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/823487 ,  H01L27/0255 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861 ,  H01L29/872 ,  H01L29/8725

摘要： This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.

公开(公告)号：US09991380B2

公开(公告)日：2018-06-05

申请号：US15632204

申请日：2017-06-23

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Madhur Bobde ,  Lingpeng Guan ,  Karthik Padmanabhan ,  Hamza Yilmaz

IPC分类号： H01L29/94 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7816

摘要： A lateral superjunction MOSFET device includes multiple transistor cells connected to a lateral superjunction structure, each transistor cell including a conductive gate finger, a source region finger, a body contact region finger and a drain region finger arranged laterally within each transistor cell. Each of the drain region fingers, the source region fingers and the body contact region fingers is a doped region finger having a termination region at an end of the doped region finger. The lateral superjunction MOSFET device further includes a termination structure formed in the termination region of each doped region finger and including one or more termination columns having the same conductivity type as the doped region finger and positioned near the end of the doped region finger. The one or more termination columns extend through the lateral superjunction structure and are electrically unbiased.

公开(公告)号：US09960664B2

公开(公告)日：2018-05-01

申请号：US15240787

申请日：2016-08-18

申请人： Alpha and Omega Semiconductor (Cayman) Ltd.

发明人： Tien-Chi Lin ,  Yu-Ming Chen ,  Jung-Pei Cheng ,  Yung-Chuan Hsu ,  Yueh-Ping Yu ,  Wei-Ting Wang ,  Pei-Lun Huang

IPC分类号： H02M3/335 ,  H02M1/08 ,  H02M1/40 ,  H02M1/00 ,  H02M1/36

CPC分类号： H02M1/08 ,  H02M1/36 ,  H02M1/40 ,  H02M3/33523 ,  H02M3/33592 ,  H02M2001/0006 ,  H02M2001/0009 ,  Y02B70/1475

摘要： A voltage converter comprises a second controller as a power switch of the secondary side of the transformer for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage and generating a control signal, and a coupling element for transmitting the control signal generated by the second controller to the first controller on the primary side of the transformer enabling the first controller to generate a first pulse signal driving the power switch to control the on/off state of the primary side winding.

公开(公告)号：US09893209B2

公开(公告)日：2018-02-13

申请号：US14276995

申请日：2014-05-13

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hideaki Tsuchiko

IPC分类号： H01L29/808 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L29/40 ,  H01L29/06

CPC分类号： H01L29/66893 ,  H01L21/76264 ,  H01L29/0692 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/402 ,  H01L29/66901 ,  H01L29/808

摘要： A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage.

公开(公告)号：US09853143B2

公开(公告)日：2017-12-26

申请号：US15095426

申请日：2016-04-11

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Shekar Mallikarjunaswamy

IPC分类号： H01L29/78 ,  H01L29/45 ,  H01L29/06 ,  H01L29/49 ,  H01L29/417 ,  H01L29/66 ,  H01L23/532 ,  H01L23/535 ,  H01L29/10 ,  H01L21/28

CPC分类号： H01L29/7816 ,  H01L21/28052 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7835

摘要： A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body contacts. The polysilicon gate mesh can be formed using minimum polysilicon-to-polysilicon spacing to minimize the cell pitch of the cellular transistor array.

公开(公告)号：US09837400B2

公开(公告)日：2017-12-05

申请号：US15258759

申请日：2016-09-07

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Shekar Mallikarjunaswamy

IPC分类号： H01L27/085 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/808 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L21/8232 ,  H01L21/265

CPC分类号： H01L27/085 ,  H01L21/26513 ,  H01L21/8232 ,  H01L21/8234 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/66901 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7823 ,  H01L29/808

摘要： A power integrated circuit includes a double-diffused metal-oxide-semiconductor (LDMOS) transistor formed in a first portion of the semiconductor layer with a channel being formed in a first body region. The power integrated circuit includes a first deep diffusion region formed in the first deep well under the first body region and in electrical contact with the first body region and a second deep diffusion region formed in the first deep well under the drain drift region and in electrical contact with the first body region. The first deep diffusion region and the second deep diffusion region together form a reduced surface field (RESURF) structure in the LDMOS transistor.