公开(公告)号：US6066572A

公开(公告)日：2000-05-23

申请号：US241338

申请日：1999-02-01

申请人： Le-Yen Lu ,  Yau-Kae Sheu

发明人： Le-Yen Lu ,  Yau-Kae Sheu

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/316 ,  H01L21/02

CPC分类号： H01L21/02046 ,  H01L21/02052 ,  H01L21/28167 ,  H01L21/28211 ,  H01L21/31116 ,  H01L21/31662 ,  Y10S438/906 ,  Y10S438/974

摘要： A method of removing carbon contamination. On a semiconductor substrate having carbon contamination thereon, a sacrificial oxide layer is formed. During the formation of the sacrificial oxide layer, an agent is introduced to help and improve the growth of the sacrificial oxide layer, and to trap the carbon contamination. The sacrificial oxide layer is then removed, and the carbon contamination is removed with the sacrificial oxide layer.

摘要翻译： 一种去除碳污染的方法。 在其上具有碳污染的半导体衬底上形成牺牲氧化物层。 在牺牲氧化物层的形成期间，引入试剂以帮助和改善牺牲氧化物层的生长，并捕获碳污染。 然后去除牺牲氧化物层，并用牺牲氧化物层除去碳污染物。

公开(公告)号：US6066419A

公开(公告)日：2000-05-23

申请号：US270278

申请日：1999-03-16

申请人： Cheng-Kuan Wu ,  Te-Yang Fang

发明人： Cheng-Kuan Wu ,  Te-Yang Fang

IPC分类号： G03F7/20 ,  G03F9/00

CPC分类号： G03F7/70558 ,  G03F7/70625 ,  G03F7/70641

摘要： A method for monitoring dosage/focus/leveling is provided. A control wafer is provided and divided into several regions. Five of the regions near the center of the wafer are used to monitor normally. Other regions are used as dummy shots. When a situation of a stepper changes greatly, the dosage/focus/leveling of the control wafer is monitored using the dummy shots. In monitoring exposure dosage, the middlemost region is monitored. One of the five regions, which is the most central, is exposed with a low exposure energy to enhance sensitivity of critical dimension versus energy. Many points with small areas are developed in the centermost region to take sufficient samples. Since the developed points are close, effects from the nonuniformity of development and from the nonuniformity of the photoresist layer are prevented. In focus/leveling monitoring, a curve diagram of exposure dosage versus critical dimension is provided. An exposure parameter is taken at a range of the curve with a large slope. The focus/leveling is monitored at the other four regions near the middlemost region.

摘要翻译： 提供了一种用于监测剂量/焦点/流平的方法。 控制晶片被提供并分成几个区域。 晶圆中心附近的五个区域用于正常监测。 其他区域用作虚拟镜头。 当步进器的情况发生很大变化时，使用虚拟镜头监视控制晶片的剂量/焦点/调平。 在监测暴露剂量时，监测中间区域。 最中心的五个地区之一暴露于低暴露能量，以提高关键尺寸与能量的敏感性。 在最中心地区开发了许多具有小面积的点以获取足够的样品。 由于显影点靠近，因此防止了光刻胶层的不均匀性和不均匀性的影响。 在焦点/调平监测中，提供了暴露剂量与临界尺寸的曲线图。 在具有大斜率的曲线的范围内拍摄曝光参数。 在最中心区域附近的其他四个地区监测焦点/平整度。

公开(公告)号：US6060366A

公开(公告)日：2000-05-09

申请号：US58579

申请日：1998-04-10

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/02 ,  H01L21/20

CPC分类号： H01L28/92 ,  H01L28/55

摘要： A method for forming a DRAM capacitor comprising the steps of first depositing conductive material over a dielectric layer and into a contact opening already formed in the dielectric layer, then patterning the conductive layer using a photoresist layer. Next, a portion of the photoresist layer is removed to expose a peripheral strip on the upper surface of the conductive layer. Then, a liquid-phase deposition method is used to deposit a silicon oxide layer over the conductive layer and the dielectric layer. Due to the selectivity of liquid-phase deposition method, none of the silicon oxide layer is deposited over the photoresist layer. Hence, after the removal of the photoresist layer, the silicon oxide layer can be used as a mask for patterning the conductive layer again. The patterned conductive layer then becomes the cylindrical-shaped storage electrode of a DRAM capacitor.

摘要翻译： 一种用于形成DRAM电容器的方法，包括以下步骤：首先在电介质层上沉积导电材料并将其形成在已经形成在电介质层中的接触开口中，然后使用光致抗蚀剂层图案化导电层。 接下来，去除光致抗蚀剂层的一部分以暴露导电层的上表面上的周边条。 然后，使用液相沉积方法在导电层和电介质层上沉积氧化硅层。 由于液相沉积方法的选择性，在光致抗蚀剂层上没有沉积氧化硅层。 因此，在去除光致抗蚀剂层之后，氧化硅层可以用作再次用于图案化导电层的掩模。 图案化导电层然后变成DRAM电容器的圆柱形存储电极。

公开(公告)号：US6017796A

公开(公告)日：2000-01-25

申请号：US138757

申请日：1998-08-24

申请人： Hwi-Huang Chen ,  Gary Hong

发明人： Hwi-Huang Chen ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L27/11521

摘要： A semiconductor fabrication method for fabricating a flash EEPROM (electrically erasable and programmable read-only memory) device uses STI (shallow-trench isolation) technique to form the field oxide isolation layers so as to make the EEPROM device suitable for fabrication at the submicron level of integration. By this method, the first step is to prepare a semiconductor substrate. Next, a plurality of field oxide isolation layers are formed through the STI technique to define active region in the substrate. After this, at least one gate structure is formed within the active region, which includes a tunnel oxide layer, a first conductive layer serving as a floating gate, a dielectric layer, a second conductive layer serving as a control gate, and a topping layer. Subsequently, an ion-implantation process is performed to form source/drain regions beside the gate structure. A sidewall spacer is then formed on the sidewall of the gate structure. Next, a metallization layer is formed over the entire substrate and then an insulating layer is formed over the metallization layer. The insulating layer is then selectively removed in such a manner that the remaining part thereof covers the source region and the field oxide isolation layers neighboring the source region. Finally, all the part of the metallization layer that is uncovered by the remaining part of the insulating layer is entirely removed.

摘要翻译： 用于制造闪速EEPROM（电可擦除可编程只读存储器）器件的半导体制造方法使用STI（浅沟槽隔离）技术形成场氧化物隔离层，以使得EEPROM器件适合于在亚微米级制造 的整合。 通过该方法，第一步是制备半导体衬底。 接下来，通过STI技术形成多个场氧化物隔离层，以限定衬底中的有源区。 此后，在有源区域内形成至少一个栅极结构，该有源区包括隧道氧化物层，用作浮置栅极的第一导电层，介电层，用作控制栅极的第二导电层，以及顶层 。 随后，进行离子注入工艺以在栅极结构旁边形成源/漏区。 然后在栅极结构的侧壁上形成侧壁间隔物。 接下来，在整个基板上形成金属化层，然后在金属化层上形成绝缘层。 然后选择性地去除绝缘层，使得其余部分覆盖与源极区域相邻的源极区域和场氧化物隔离层。 最后，完全除去金属化层未被绝缘层的剩余部分覆盖的部分。

公开(公告)号：US6008522A

公开(公告)日：1999-12-28

申请号：US113844

申请日：1998-07-10

申请人： Gary Hong ,  Yau-Kae Sheu ,  Wenchi Ting

发明人： Gary Hong ,  Yau-Kae Sheu ,  Wenchi Ting

IPC分类号： H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/112 ,  H01L29/76

CPC分类号： H01L27/10844 ,  H01L27/10805 ,  H01L27/112 ,  H01L27/11213 ,  Y10S257/91

摘要： The structure of a buried bit line. A substrate is provided and a trench is, formed within the substrate. Next, a trench insulating layer is located on a portion of the trench surface to expose a top corner of the trench. Then, a first conductive layer is fills the trench and forms a surface. Afterwards, a second conductive layer is formed on the surface and fills the trench, wherein the second conductive layer makes contact with the top corner, and a shallow junction region is located at the top corner and makes contact with the second conductive layer.

摘要翻译： 埋地线的结构。 提供衬底并且在衬底内形成沟槽。 接下来，沟槽绝缘层位于沟槽表面的一部分上以暴露沟槽的顶角。 然后，第一导电层填充沟槽并形成表面。 之后，在表面上形成第二导电层并填充沟槽，其中第二导电层与顶角接触，并且浅结区位于顶角处并与第二导电层接触。

公开(公告)号：US6001707A

公开(公告)日：1999-12-14

申请号：US241760

申请日：1999-02-01

申请人： Chih-Hung Lin ,  Gary Hong

发明人： Chih-Hung Lin ,  Gary Hong

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/76237

摘要： A method for forming a shallow trench isolation structure in a substrate includes the steps of forming a doped region around the future top corner regions of a trench. The concentration of dopants inside the doped region increases towards the substrate surface. Thereafter, a trench is formed in the substrate, and then a thermal oxidation operation is carried out. Utilizing the higher oxidizing rate for doped substrate relative to an undoped region, the upper corners of the trench become rounded corners. Subsequently, a liner oxide layer is formed over the substrate surface inside the trench using conventional methods. Finally, insulating material is deposited into the trench to form a trench isolation structure.

摘要翻译： 在衬底中形成浅沟槽隔离结构的方法包括以下步骤：在沟槽的未来顶角区域周围形成掺杂区域。 掺杂区内掺杂剂的浓度朝向衬底表面增加。 之后，在衬底中形成沟槽，然后进行热氧化操作。 利用掺杂衬底相对于未掺杂区域的较高氧化速率，沟槽的上角变成圆角。 随后，使用常规方法在沟槽内的衬底表面上形成衬里氧化物层。 最后，将绝缘材料沉积到沟槽中以形成沟槽隔离结构。

公开(公告)号：US5981337A

公开(公告)日：1999-11-09

申请号：US70374

申请日：1998-04-30

申请人： Shu-Ya Chuang

发明人： Shu-Ya Chuang

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90

摘要： A method of fabricating a stack capacitor. Using self-aligned method by the formation of spacers on the poly-silicon layer, a stack capacitor is formed by using photo-lithography and etching only once.

摘要翻译： 一种制造堆叠电容器的方法。 使用通过在多晶硅层上形成间隔物的自对准方法，通过使用光刻和蚀刻仅形成一个堆叠电容器。

公开(公告)号：US5937309A

公开(公告)日：1999-08-10

申请号：US241977

申请日：1999-02-01

申请人： Shu-Ya Chuang

发明人： Shu-Ya Chuang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  Y10S148/05 ,  Y10S148/161 ,  Y10S438/978

摘要： A method for fabricating a shallow trench isolation (STI) structure in a semiconductor substrate. A stop layer is formed on the substrate and a first sacrificial layer is formed on the stop layer. The first sacrificial layer and the stop layer are defined to form an opening on the substrate. A conformal second sacrificial layer with rounded corners is formed on the substrate. The second sacrificial layer, the first sacrificial layer, and a portion of the substrate are anisotropically removed to form a trench in the substrate using the stop layer as a removal stop layer. The substrate is over removed using the stop layer as a mask layer so that spacers of the second sacrificial layer are remained on the substrate to cover portions of sidewalls of the stop layer.

摘要翻译： 一种在半导体衬底中制造浅沟槽隔离（STI）结构的方法。 在基板上形成停止层，在停止层上形成第一牺牲层。 第一牺牲层和止挡层被限定为在基底上形成开口。 在基板上形成具有圆角的保形第二牺牲层。 各向异性去除第二牺牲层，第一牺牲层和衬底的一部分，以使用停止层作为去除停止层在衬底中形成沟槽。 使用停止层作为掩模层将衬底去除，使得第二牺牲层的间隔物保留在衬底上以覆盖停止层的侧壁的部分。

公开(公告)号：US5937298A

公开(公告)日：1999-08-10

申请号：US957811

申请日：1997-10-27

申请人： Tsung-Yuan Hung ,  Yao-Pi Hsu

发明人： Tsung-Yuan Hung ,  Yao-Pi Hsu

IPC分类号： H01L21/336 ,  H01L27/02

CPC分类号： H01L29/66659 ,  H01L27/0266 ,  H01L29/665

摘要： A method for forming electrostatic discharge protection devices that includes the steps of forming a transistor, which comprises a gate, a source region, a drain region, on a semiconductor substrate. Then, an insulating layer is formed over the transistor. Next, the insulating layer above the gate is removed, which represents one characteristic of this invention. Subsequently, a photolithographic processing operation is performed to form a photoresist layer over the substrate. The photoresist layer covers the insulating layer above the gate and the drain region while exposing the insulating layer above the source region. Thereafter, using the photoresist layer as a mask, the exposed insulating layer above the source region is removed. Next, the photoresist layer is removed. Finally, a self-aligned silicide processing operation is performed to form a silicide layer over the gate and the source region. Since no silicide layer is formed over the drain terminal, burnout of the drain terminal due to overheating can be avoided.

摘要翻译： 一种用于形成静电放电保护器件的方法，包括在半导体衬底上形成包括栅极，源极区域，漏极区域的晶体管的步骤。 然后，在晶体管上形成绝缘层。 接下来，去除栅极上方的绝缘层，这代表本发明的一个特征。 随后，进行光刻处理操作以在衬底上形成光致抗蚀剂层。 光致抗蚀剂层在栅极和漏极区域上方覆盖绝缘层，同时使源区域上方的绝缘层暴露。 此后，使用光致抗蚀剂层作为掩模，去除源区域上方的暴露的绝缘层。 接下来，去除光致抗蚀剂层。 最后，进行自对准的硅化物处理操作以在栅极和源极区域上形成硅化物层。 由于在漏极端子上没有形成硅化物层，所以可以避免由于过热引起的漏极端子的烧坏。

公开(公告)号：US5932910A

公开(公告)日：1999-08-03

申请号：US998772

申请日：1997-12-29

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521

摘要： This invention provides a flash memory cell structure comprising a semiconductor substrate; a tunneling oxide layer formed above the substrate and having a long narrow top profile; a gate oxide layer formed above the substrate on each side of the tunneling oxide layer; a bottom conductive layer formed above the substrate and surrounded the gate oxide layer; and a stacked gate formed above the tunneling oxide layer, the gate oxide layer and the bottom conductive layer, wherein there is an insulating layer between the stacked gate and the bottom conductive layer for electrically isolating the stacked gate from the bottom conductive layer, and that the stacked gate further comprises a floating gate, a dielectric layer and a control gate.

摘要翻译： 本发明提供了一种包括半导体衬底的闪存单元结构; 在衬底上形成并具有长的窄的顶部轮廓的隧道氧化物层; 在隧道氧化物层的每一侧的衬底上形成的栅氧化层; 底部导电层，形成在衬底上并包围栅极氧化物层; 以及形成在隧道氧化物层，栅极氧化物层和底部导电层上方的堆叠栅极，其中在堆叠的栅极和底部导电层之间存在用于将堆叠的栅极与底部导电层电隔离的绝缘层，并且 堆叠栅极还包括浮置栅极，电介质层和控制栅极。