公开(公告)号：US20090068797A1

公开(公告)日：2009-03-12

申请号：US12270642

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H01L21/50

CPC classification number: H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having a plurality of recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer is between the chips and the conductive layer. The chips are electrically connected to the conductive layer by a plurality of bonding wires. At least one molding compound is formed to encapsulate the conductive layer, the patterned solder resist layer, the chips and the bonding wires. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Then, the molding compound and the patterned conductive layer are separated.

Abstract translation: 提供了一种用于四边形扁平无铅（QFN）芯片封装结构的制造工艺。 首先，提供在导电层上具有多个凹部的导电层和图案化阻焊层，其中图案化的阻焊层覆盖导电层的凹部。 多个芯片被结合到图案化的阻焊层上，使得图案化的阻焊层位于芯片和导电层之间。 芯片通过多根接合线与导电层电连接。 形成至少一种模塑料以封装导电层，图案化阻焊层，芯片和接合线。 去除由图案化的阻焊层未覆盖的导电层的一部分，以便形成图案化的导电层。 然后，分离模塑料和图案化导电层。

公开(公告)号：US20090068793A1

公开(公告)日：2009-03-12

申请号：US12270627

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H01L21/50

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/4951 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a first patterned solder resist layer on the patterned conductive layer are provided. A second patterned solder resist layer is formed on the patterned conductive layer such that the first patterned solder resist layer and the second patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. Chips are bonded onto the first patterned solder resist layer such that the first patterned solder resist layer is between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings. At least one molding compound is formed and the molding compound, the first patterned solder resist layer and the second patterned solder resist layer are separated.

Abstract translation: 提供了一种用于芯片封装结构的制造工艺。 首先，提供在图案化导电层上具有多个第一开口和第一图案化阻焊层的图案化导电层。 在图案化导电层上形成第二图案化阻焊层，使得第一图案化阻焊层和第二图案化阻焊层设置在图案化导电层的两个相对表面处。 芯片被结合到第一图案化阻焊层上，使得第一图案化阻焊层位于芯片和图案化导电层之间。 芯片通过穿过第一开口的多个接合线电连接到图案化的导电层。 形成至少一种模塑料，并且分离模塑料，第一图案化阻焊层和第二图案化阻焊层。

公开(公告)号：US20080258279A1

公开(公告)日：2008-10-23

申请号：US11934287

申请日：2007-11-02

Applicant: Chun Ying Lin ,  Geng Shin Shen ,  Yu Tang Pan ,  Shih Wen Chou

Inventor： Chun Ying Lin ,  Geng Shin Shen ,  Yu Tang Pan ,  Shih Wen Chou

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L21/4842 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K3/3426 ,  H05K2201/09745 ,  H05K2201/10689 ,  H05K2201/10787 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

Abstract translation: 由无引线封装采用的引线框架包括多个封装单元和胶带。 每个封装单元具有带有多个开口的管芯焊盘和设置在多个开口中的多个销。 粘合带粘附到多个封装单元的表面并固定芯片焊盘和多个引脚。

公开(公告)号：US20080157626A1

公开(公告)日：2008-07-03

申请号：US11797243

申请日：2007-05-02

Applicant: Alex Horng ,  I-Yu Huang ,  Yen-Chi Lee ,  Chun-Ying Lin

Inventor： Alex Horng ,  I-Yu Huang ,  Yen-Chi Lee ,  Chun-Ying Lin

IPC: H02N11/00

CPC classification number: H02N1/002

Abstract: To improve the yield, lifetime and driving voltage of the micro scratch drive actuator (SDA), this invention proposes a novel layout design including the etch holes and flange structure designs.Once the etch holes added to the layout of conventional SDA plate, the releasing of structure layer can be accelerated and the accumulated residual charges in the front end of SDA plate is reduced. In this innovative design, a longer lifetime and lower driving voltage of the SDA device can be achieved. On the other hand, adding the flange structure design in the corner of the beam-to-plate conjunction can improve the flexural rigidity of the narrow polysilicon supporting beam which will further enhance the yield of the SDA device and reduce the crack failure under actuating situation.

Abstract translation: 为了提高微刮擦驱动执行器（SDA）的产量，寿命和驱动电压，本发明提出了一种新颖的布局设计，包括蚀刻孔和法兰结构设计。 一旦添加到常规SDA板的布局中的蚀刻孔，可以加速结构层的释放，并减少SDA板的前端中累积的残留电荷。 在这种创新设计中，可以实现SDA器件寿命更长，驱动电压更低。 另一方面，将法兰结构设计添加到梁对板连接的角部可以提高窄多晶硅支撑梁的抗弯刚度，这将进一步提高SDA装置的产量，并减少启动情况下的裂纹破坏 。

公开(公告)号：US20080157625A1

公开(公告)日：2008-07-03

申请号：US11790718

申请日：2007-04-27

Applicant: Alex Horng ,  I-Yu Huang ,  Yen-Chi Lee ,  Chun-Ying Lin

Inventor： Alex Horng ,  I-Yu Huang ,  Yen-Chi Lee ,  Chun-Ying Lin

IPC: H02N11/00 ,  C01B33/02 ,  H01H57/00

CPC classification number: H02N1/002 ,  H02K7/14

Abstract: Based on the voltage-division theory, this invention proposes a new method to decrease the driving voltage of the micro scratch drive actuator (SDA) by using an ultra-low resistivity silicon wafer as substrate. This patent has compared two SDA actuators with the same layout and fabricating processes but under different resistivity of substrate. The SDA fabricated on the ultra-low resistivity silicon wafer has demonstrated a lower driving voltage of only about 4˜12 Vo-p. However, the conventional SDA using normal silicon wafer needs higher driving voltage (30˜75 Vo-p), thus has lower probability for commercial applications. On the other hand, this invention presents a new SDA process to overcome the inherent 2 μm line-width limitation of conventional mask aligner with 4360 Å UV wavelength light source (g-line) and further to reduce the driving voltage of SDA.

Abstract translation: 基于分压理论，本发明提出了一种通过使用超低电阻率硅晶片作为衬底来降低微刮擦驱动致动器（SDA）的驱动电压的新方法。 该专利比较了具有相同布局和制造工艺但在不同电阻率的基板上的两个SDA致动器。 在超低电阻率硅晶片上制造的SDA已经表现出较低的驱动电压仅为约4〜12V o-p 。 然而，使用普通硅晶片的常规SDA需要较高的驱动电压（30〜75V o-p），因此对于商业应用具有较低的概率。 另一方面，本发明提出了一种新的SDA方法，以克服具有4360A紫外线波长光源（g-line）的常规掩模对准器的固有2 mum线宽限制，并进一步降低SDA的驱动电压。

公开(公告)号：US20070088747A1

公开(公告)日：2007-04-19

申请号：US11307796

申请日：2006-02-22

Applicant: Chih-Chuan Cheng ,  Tsai-Chuang Wang ,  Chun-Ying Lin

Inventor： Chih-Chuan Cheng ,  Tsai-Chuang Wang ,  Chun-Ying Lin

IPC: G06F17/00

CPC classification number: G06F16/4387 ,  G06F16/48

Abstract: An automatic multimedia searching method and the multimedia downloading system thereof are provided, which are capable of increasing user's convenience on multimedia searching and downloading events. The method includes the following steps. First, an electronic device which stores a multimedia file and a data source connection are provided. Next, a multimedia file is played. When playing the multimedia file, the electronic device automatically searches the data source for multimedia files having the same content as the content of the information tag in the multimedia file. Finally, the found multimedia files are displayed on the electronic device.

Abstract translation: 提供了一种自动多媒体搜索方法及其多媒体下载系统，其能够增加用户对多媒体搜索和下载事件的便利。 该方法包括以下步骤。 首先，提供存储多媒体文件和数据源连接的电子装置。 接下来，播放多媒体文件。 当播放多媒体文件时，电子设备自动搜索具有与多媒体文件中的信息标签的内容相同内容的多媒体文件的数据源。 最后，找到的多媒体文件显示在电子设备上。

公开(公告)号：US20060110570A1

公开(公告)日：2006-05-25

申请号：US11284478

申请日：2005-11-22

Applicant: Ru-Lin Yeh ,  Chung-Fa Chen ,  Chun-Ying Lin ,  Wei-Hsiang Wang

Inventor： Ru-Lin Yeh ,  Chung-Fa Chen ,  Chun-Ying Lin ,  Wei-Hsiang Wang

IPC: B32B3/02

CPC classification number: G11B7/244 ,  G11B7/24038 ,  G11B7/243 ,  G11B7/2467 ,  G11B7/2472 ,  G11B7/2534 ,  G11B7/258 ,  G11B7/26 ,  G11B2007/2431 ,  G11B2007/24312

Abstract: A dual-layer recordable optical disc includes a first recording layer and a second recording layer disposed on the first recording layer. The first recording layer is made of organic material, and the second recording layer is made of inorganic material. The optical disc may further includes a first substrate, a second substrate and a bonding layer. The first recording layer includes a dye recording layer disposed on the first substrate, and a first reflection layer disposed on the dye recording layer, whereas the second recording layer includes an inorganic recording layer and a second reflection layer disposed on the inorganic recording layer. In addition, the second substrate is disposed on the second reflection layer, and the bonding layer is disposed between the first reflection layer and the inorganic recording layer. A manufacturing process of the optical disc is also provided to increase production yield and lower manufacturing cost.

Abstract translation: 双层可记录光盘包括设置在第一记录层上的第一记录层和第二记录层。 第一记录层由有机材料制成，第二记录层由无机材料制成。 光盘还可以包括第一基板，第二基板和接合层。 第一记录层包括设置在第一基板上的染料记录层和设置在染料记录层上的第一反射层，而第二记录层包括设置在无机记录层上的无机记录层和第二反射层。 此外，第二基板设置在第二反射层上，并且接合层设置在第一反射层和无机记录层之间。 还提供了光盘的制造工艺以提高产量并降低制造成本。

公开(公告)号：US06961302B2

公开(公告)日：2005-11-01

申请号：US10065679

申请日：2002-11-08

Applicant: Shyh-yeu Wang ,  Biing-Hwang Lin ,  Chun-Ying Lin

Inventor： Shyh-yeu Wang ,  Biing-Hwang Lin ,  Chun-Ying Lin

IPC: G11B7/09 ,  G11B7/24 ,  G11B7/246 ,  G11B7/2472 ,  G11B7/257 ,  G11B7/258 ,  G11B7/26

CPC classification number: G11B7/246 ,  G11B7/0938 ,  G11B7/24 ,  G11B7/2472 ,  G11B7/248 ,  G11B7/257 ,  G11B7/258 ,  G11B2007/2571 ,  G11B2007/25711 ,  G11B2007/25713 ,  G11B2007/25715 ,  G11B2007/25716 ,  Y10T428/21

Abstract: A method and structure for intensifying track seeking signals from an optical disk, in particular, a recordable digital versatile disk (DVD-R). With the addition of an optical correction layer between a dye material layer and a reflection layer inside the DVD-R, track-seeking signals of the optical disk are intensified and recording quality of the optical disk is improved. The optical correction layer is a transparent or semi-transparent layer made from inorganic materials. The optical correction layer is formed over the dye material layer in a sputtering process.

Abstract translation: 一种用于从光盘，特别是可记录数字通用盘（DVD-R）增强追踪信号的方法和结构。 通过在DVD-R内部的染料材料层和反射层之间添加光学校正层，光盘的追踪信号被增强，并且提高了光盘的记录质量。 光学校正层是由无机材料制成的透明或半透明层。 在溅射工艺中，在染料材料层上形成光学校正层。

公开(公告)号：US08048778B1

公开(公告)日：2011-11-01

申请号：US12964964

申请日：2010-12-10

Applicant: Chin-Yu Ku ,  Hsiu-Mei Yu ,  Chun-Ying Lin ,  Young-Chang Lien ,  Sheng-Hsiang Chiu ,  Ta-Jen Yu

Inventor： Chin-Yu Ku ,  Hsiu-Mei Yu ,  Chun-Ying Lin ,  Young-Chang Lien ,  Sheng-Hsiang Chiu ,  Ta-Jen Yu

IPC: H01L21/00

CPC classification number: H01L21/78 ,  B23K26/0006 ,  B23K26/009 ,  B23K26/18 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  H01L23/585 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/013

Abstract: An embodiment of the disclosure includes a method of dicing a semiconductor structure. A device layer on a semiconductor substrate is provided. The device layer has a first chip region and a second chip region. A scribe line region is between the first chip region and the second chip region. A protective layer is formed over the device layer thereby over the semiconductor substrate. The protective layer on the scribe line region is laser sawn to form a notch. The notch extends into the semiconductor substrate and the protective layer is formed to cover a portion of the notch. A mechanically sawing is performed through the portion of the protective layer and the substrate to separate the first chip region and the second chip region.

Abstract translation: 本公开的实施例包括切割半导体结构的方法。 提供半导体衬底上的器件层。 器件层具有第一芯片区域和第二芯片区域。 划线区域在第一芯片区域和第二芯片区域之间。 在器件层上形成保护层，从而在半导体衬底上形成保护层。 切割线区域上的保护层被激光锯切以形成切口。 凹口延伸到半导体衬底中，形成保护层以覆盖凹口的一部分。 通过保护层和衬底的部分进行机械锯切以分离第一芯片区域和第二芯片区域。

公开(公告)号：US07642137B2

公开(公告)日：2010-01-05

申请号：US11746654

申请日：2007-05-10

Applicant: Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

Inventor： Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

IPC: H01L21/44

CPC classification number: H01L21/563 ,  H01L23/3135 ,  H01L24/97 ,  H01L33/642 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip package including a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer is provided. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.

Abstract translation: 包括热增强板的芯片封装，在热增强板周围接触并与热增强板电绝缘，设置在触点和热增强板上的膜状电路层，导电粘合剂层，第一模制件和 提供设置在膜状电路层上的至少一个芯片。 导电性粘合剂层设置在触点和通过导电粘合剂层与触点电连接的膜状电路层之间。 芯片具有背面，有源表面和设置在其上的许多凸块，并且芯片经由凸块电连接到膜状电路层。 第一模制品至少封装热增强板的一部分，导电粘合剂层，触点的一部分和膜状电路层的至少一部分。 因此，提高了发光芯片封装的散热效率。