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    Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit
    12.
    发明授权
    Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit 有权
    集成电路加热器，用于减少集成电路材料中的应力和集成电路的芯片引线，并优化集成电路器件的性能

    公开(公告)号：US09318409B1

    公开(公告)日：2016-04-19

    申请号：US14496870

    申请日：2014-09-25

    申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    IPC分类号： H01L21/66 ,  H01L23/34

    CPC分类号： H01L25/065 ,  G01K7/00 ,  G01K7/427 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.

    摘要翻译： 一种包括第一检测器的装置，包括输出，设置在集成电路芯片的第一位置并且被配置为确定第一温度信息，芯片加热器，包括用于接收控制信号的输入端，所述芯片加热器设置在所述第一温度信息的第二位置处 集成电路并且被配置为基于所述控制信号加热包括所述第一位置和所述第二位置的所述集成电路装置的区域;以及加热器控制器，包括耦合到所述第一检测器的输出的第一输入以接收所述第一温度 信息和耦合到芯片加热器的输入的输出，加热器控制器被配置为基于第一温度信息生成控制信号。

    INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT
    13.
    发明申请
    INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT 有权
    用于集成电路集成电路材料和芯片引线的集成电路加热器，并优化集成电路器件的性能

    公开(公告)号：US20160093549A1

    公开(公告)日：2016-03-31

    申请号：US14496870

    申请日：2014-09-25

    申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    IPC分类号： H01L23/34

    CPC分类号： H01L25/065 ,  G01K7/00 ,  G01K7/427 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.

    摘要翻译： 一种包括第一检测器的装置，包括输出，设置在集成电路芯片的第一位置并且被配置为确定第一温度信息，芯片加热器，包括用于接收控制信号的输入端，所述芯片加热器设置在所述第一温度信息的第二位置处 集成电路并且被配置为基于所述控制信号加热包括所述第一位置和所述第二位置的所述集成电路装置的区域;以及加热器控制器，包括耦合到所述第一检测器的输出的第一输入以接收所述第一温度 信息和耦合到芯片加热器的输入的输出，加热器控制器被配置为基于第一温度信息生成控制信号。

    Method for forming a packaged semiconductor device
    14.
    发明授权
    Method for forming a packaged semiconductor device 有权
    用于形成封装的半导体器件的方法

    公开(公告)号：US09134366B2

    公开(公告)日：2015-09-15

    申请号：US14011160

    申请日：2013-08-27

    申请人： Sergio A. Ajuria ,  Phuc M. Nguyen ,  Douglas M. Reber

    发明人： Sergio A. Ajuria ,  Phuc M. Nguyen ,  Douglas M. Reber

    IPC分类号： H01L21/66 ,  G01R31/28 ,  H01L23/522

    CPC分类号： G01R31/2884 ,  G01R31/2896 ,  H01L22/32 ,  H01L23/5226 ,  H01L24/19 ,  H01L2224/13

    摘要： A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.

    摘要翻译： 制造封装半导体器件的方法包括将多个单片化半导体管芯集成在管芯载体中，并在管芯载体上形成一个或多个互连层。 互连层包括耦合到多个单片半导体管芯上的接触焊盘的导电层内结构和层间结构中的至少一个。 一组着陆焊盘通过第一组导电层内结构和层间结构形成为耦合到接触焊盘的第一子集。 通过第二组导电层内结构和层间结构，形成耦合到接触焊盘的第二子集的一组探针焊盘。 将管芯载体分离以形成多个封装的半导体器件。 在分离模具载体期间移除探针焊盘组。

    Method and apparatus to improve reliability of vias
    16.
    发明授权
    Method and apparatus to improve reliability of vias 有权
    提高通孔可靠性的方法和装置

    公开(公告)号：US08703507B1

    公开(公告)日：2014-04-22

    申请号：US13630996

    申请日：2012-09-28

    申请人： Douglas M. Reber

    发明人： Douglas M. Reber

    IPC分类号： G01R31/26 ,  H01L21/66

    CPC分类号： G06F17/5068 ,  G06F2217/72 ,  H01L21/76814 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

    摘要： A semiconductor device comprising a first insulating layer, a first metal conductor layer formed over the first insulating layer, a second insulating layer comprising a low-k insulating material formed over the first metal conductor, a second metal conductor layer formed over the second insulating layer, vias formed in the second insulating layer connecting the first metal conductor layer to the second metal conductor layer, and a plurality of metal lines. One of the metal lines is expanded around one of the vias compared to metal lines around other ones of the vias so that predetermined areas around each of the vias meets a minimum metal density.

    摘要翻译： 一种半导体器件，包括第一绝缘层，形成在第一绝缘层上的第一金属导体层，包含形成在第一金属导体上的低k绝缘材料的第二绝缘层，形成在第二绝缘层上的第二金属导体层 形成在连接第一金属导体层和第二金属导体层的第二绝缘层中的通孔，以及多个金属线。 与围绕其他通孔的金属线相比，其中一条金属线扩展到其中一条通孔，使得每个通孔周围的预定区域达到最小金属密度。

    METHODS AND APPARATUS TO IMPROVE RELIABILITY OF ISOLATED VIAS
    19.
    发明申请
    METHODS AND APPARATUS TO IMPROVE RELIABILITY OF ISOLATED VIAS 有权
    提高隔离可靠度的方法和装置

    公开(公告)号：US20130134595A1

    公开(公告)日：2013-05-30

    申请号：US13305410

    申请日：2011-11-28

    申请人： DOUGLAS M. REBER

    发明人： DOUGLAS M. REBER

    IPC分类号： H01L23/48 ,  G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/72 ,  H01L21/76814 ,  H01L21/76828 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for increasing metal density around selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and increasing area of a metal layer which is above the selected isolated via and which encloses the selected isolated via within each zone to achieve a target metal density within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.

    摘要翻译： 提供了一种用于在半导体器件中选择的通孔周围增加金属密度的方法。 半导体器件包括多个通孔。 该方法包括：生成用于半导体器件的布局数据库; 识别多个通孔中的隔离通孔; 选择隔离通孔; 在每个所选择的隔离通孔周围限定区域; 并且增加在所选择的隔离通孔上方的金属层的面积，并且在每个区域内包围所选择的隔离通孔，以实现该区域内的目标金属密度。 该方法通过允许水分从通孔周围排出来提高半导体器件的可靠性。