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    METHOD OF FORMING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE
    11.
    发明申请
    METHOD OF FORMING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE 有权
    在SOI衬底上形成高性能FET和高电压FET的方法

    公开(公告)号：US20100035390A1

    公开(公告)日：2010-02-11

    申请号：US12188366

    申请日：2008-08-08

    Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

    Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

    IPC: H01L21/84

    CPC classification number: H01L21/84 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1203 ,  H01L27/1207

    Abstract: A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.

    Abstract translation: 保护绝缘体上半导体（SOI）衬底的顶部半导体层的第一部分，同时去除顶部半导体层的第二部分以暴露掩埋的绝缘体层。 形成包括位于顶部半导体层的第一部分上方的栅极电介质和栅电极的第一场效应晶体管。 暴露的掩埋绝缘体层的一部分用作第二场效应晶体管的栅极电介质。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。

    METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE
    14.
    发明申请
    METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 失效
    用于形成片上高频电静电放电装置的方法

    公开(公告)号：US20090317970A1

    公开(公告)日：2009-12-24

    申请号：US12144089

    申请日：2008-06-23

    Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC: H01L21/4763

    CPC classification number: H01L21/76808 ,  H01L21/7682 ,  H01L27/0248

    Abstract: A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench. A third dielectric layer is deposited over the second dielectric layer, wherein the third dielectric layer hermetically seals the release opening to provide electro-static discharge protection.

    Abstract translation: 描述了在集成电路上形成片上高频静电放电装置的方法。 在该方法的一个实施例中，提供了一种其上形成有多于一个电极的封盖的第一电介质层。 在封盖的第一介电层上沉积第二介电层。 第一硬掩模介电层沉积在第二介电层上。 通过第一硬掩模电介质层和第二电介质层形成腔沟槽到第一介电层，其中在两个相邻电极之间的第一电介质层中形成空腔沟槽。 至少一个通孔围绕腔沟槽形成穿过第二电介质层。 在所述至少一个通孔中的每一个周围形成金属沟槽。 在空腔沟槽上形成释放开口。 在第二电介质层上沉积第三电介质层，其中第三介电层气密地密封释放开口以提供静电放电保护。

    DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE
    15.
    发明申请
    DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 有权
    片上高频电子放电装置的设计结构

    公开(公告)号：US20090316314A1

    公开(公告)日：2009-12-24

    申请号：US12144095

    申请日：2008-06-23

    Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC: H02H9/00 ,  G06F17/50

    CPC classification number: H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.

    Abstract translation: 描述了片上高频静电放电装置的设计结构。 在一个实施例中，静电放电结构包括其中形成有多于一个电极的第一电介质层。 其中形成有多于一个电极的第二电介质层位于第一介电层的上方。 至少一个通孔将第一介电层中的多于一个的电极与第二介电层中的多于一个的电极连接。 通过第一电介质层和第二电介质层形成间隙，其中间隙在第一电介质层和第二电介质层中的两个相邻电极之间延伸。 第三电介质层设置在第二电介质层上，其中第三介电层气密地密封间隙以在集成电路上提供静电放电保护。

    Design Structure, Structure and Method for Providing an On-Chip Variable Delay Transmission Line With Fixed Characteristic Impedance
    16.
    发明申请
    Design Structure, Structure and Method for Providing an On-Chip Variable Delay Transmission Line With Fixed Characteristic Impedance 有权
    提供具有固定特性阻抗的片上可变延迟传输线的设计结构，结构和方法

    公开(公告)号：US20090315641A1

    公开(公告)日：2009-12-24

    申请号：US12144684

    申请日：2008-06-24

    Applicant: Hanyi Ding ,  Wayne H. Woods, JR.

    Inventor： Hanyi Ding ,  Wayne H. Woods, JR.

    IPC: H01P1/18

    CPC classification number: H01P9/00 ,  H01P1/184

    Abstract: A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, forming a first ground return structure that causes a first delay and a first characteristic impedance in the transmission line structure, and forming a second ground return structure that causes a second delay and a second characteristic impedance in the transmission line structure. The first delay is different from the second delay, and the first characteristic impedance is substantially the same as the second characteristic impedance.

    Abstract translation: 一种用于提供具有固定特性阻抗的片上可变延迟传输线的设计结构，结构和方法。 制造传输线结构的方法包括形成传输线结构的信号线，形成在传输线结构中引起第一延迟和第一特性阻抗的第一接地返回结构，以及形成第二接地返回结构，其导致 传输线结构中的第二延迟和第二特性阻抗。 第一延迟与第二延迟不同，第一特征阻抗基本上与第二特征阻抗相同。

    Vertical LC tank device
    17.
    发明授权
    Vertical LC tank device 失效
    垂直液相色谱槽装置

    公开(公告)号：US07564319B2

    公开(公告)日：2009-07-21

    申请号：US11859850

    申请日：2007-09-24

    Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

    Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

    IPC: H03B5/08 ,  H01F5/00 ,  H01L29/00

    CPC classification number: H03L7/099 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0641 ,  H01L27/08 ,  H01L27/0811 ,  H01L28/10 ,  H01L2924/0002 ,  H03J3/20 ,  H01L2924/00

    Abstract: An LC tack structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.

    Abstract translation: 一种LC粘结结构。 该结构包括在半导体衬底顶部的一组布线级别，从最靠近衬底的最低配线水平到离衬底最远的最高配线电平彼此堆叠的布线电平; 电感处于最高布线水平，电感器限制在最高布线水平的区域的周边内; 以及形成在基板中的变容二极管，变容二极管完全对准在最高布线水平的区域的周边。 该结构可以另外包括在最低布线电平和最高布线电平之间的布线级别的布线级中的电屏蔽。 或者，电感器包括磁芯和交替的非磁性导电金属线圈和围绕磁芯的磁性线圈。

    SYMMETRIC CAPACITOR STRUCTURE
    18.
    发明申请
    SYMMETRIC CAPACITOR STRUCTURE 审中-公开
    对称电容结构

    公开(公告)号：US20080142861A1

    公开(公告)日：2008-06-19

    申请号：US12029748

    申请日：2008-02-12

    Applicant: David S. Collins ,  Hanyi Ding ,  Kai Di Feng ,  Zhong-Xiang He ,  Xuefeng Liu

    Inventor： David S. Collins ,  Hanyi Ding ,  Kai Di Feng ,  Zhong-Xiang He ,  Xuefeng Liu

    IPC: H01L29/94

    CPC classification number: H01L27/0805

    Abstract: A structure comprising a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.

    Abstract translation: 一种包括形成在衬底内的第一掺杂区，第二掺杂区，第三掺杂区和第一浅沟槽隔离结构的结构。 第一掺杂区域包括具有第一极性的第一掺杂剂。 第二掺杂区域形成电容器的第一电极。 第三掺杂区域形成电容器的第二电极。 第二掺杂区域和第三掺杂区域中的每一个包括具有第二极性的第二掺杂剂。 第一浅沟槽隔离结构形成在第二掺杂区和第三掺杂区之间。 电容器包括主电容。 该结构包括第一寄生电容和第二寄生电容。 第一寄生电容约等于第二寄生电容。

    INTEGRATED PARALLEL PLATE CAPACITORS
    19.
    发明申请
    INTEGRATED PARALLEL PLATE CAPACITORS 有权
    集成并联板电容器

    公开(公告)号：US20070190760A1

    公开(公告)日：2007-08-16

    申请号：US11275544

    申请日：2006-01-13

    Applicant: Douglas Coolbaugh ,  Hanyi Ding ,  Ebenezer Eshun ,  Michael Gordon ,  Zhong-Xiang He ,  Anthony Stamper

    Inventor： Douglas Coolbaugh ,  Hanyi Ding ,  Ebenezer Eshun ,  Michael Gordon ,  Zhong-Xiang He ,  Anthony Stamper

    IPC: H01L21/425

    CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.

    Abstract translation: 形成在集成电路的后端的平行电容器采用与后端（具有相同材料，厚度等）的该级别上的其它互连件同时形成的导电电容器板。 使用与后端（优选双镶嵌）级别上的其它互连件相同的工艺将电容器板设置在层间电介质中。 一些版本的电容器在板中具有穿孔，并且垂直导电构件连接相同极性的所有板，从而与实心板相比增加了可靠性，节省了空间并增加了电容密度。

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