公开(公告)号：US5670803A

公开(公告)日：1997-09-23

申请号：US386721

申请日：1995-02-08

申请人： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  John Edward Cronin ,  Francis Roger White

发明人： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  John Edward Cronin ,  Francis Roger White

IPC分类号： H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786 ,  H01L23/485 ,  H01L23/528 ,  H01L29/41

CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/78642 ,  Y10S257/903

摘要： A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors ("FETs") buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed. A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.

摘要翻译： 阐述了一种三维五晶体管沟槽结构及其制造方法。 SRAM沟槽结构包括埋在单个沟槽内的四个场效应晶体管（“FET”）。 具体地说，两个FET位于沟槽的两个侧壁中的每个侧壁处，一个F​​ET设置在另一个FET的每个侧壁的上方。 同轴布线使沟槽内的FET交叉耦合，从而形成包括用于SRAM单元的存储触发器的一对交叉耦合的反相器。 第五个I / O晶体管设置在沟槽结构的顶部，并且便于接触到触发器。 还阐述了SRAM沟槽结构的具体细节及其制造方法。

公开(公告)号：US5665626A

公开(公告)日：1997-09-09

申请号：US464432

申请日：1995-06-05

申请人： John Edward Cronin

发明人： John Edward Cronin

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A chimney capacitor is formed having two plates, of which each is disposed above and contacts a corresponding electrical contact. The electrical contacts facilitate electrical access to the plates of the chimney capacitor. One of the electrical contacts may comprise part of a general wiring layer that may be used for both electrically accessing the capacitor and for general wiring within the IC chip. Formation of the chimney capacitor proceeds by first forming two electrical contacts on an integrated circuit ("IC") chip. A planar insulating layer is formed thereover, and the capacitor is formed at least partially within the planar insulating layer such that each plate is electrically connected to a corresponding electrical contact.

摘要翻译： 形成具有两个板的烟囱电容器，每个板设置在相应的电触头上方并与之相接触。 电触点便于电连接到烟囱电容器的板。 电触点中的一个可以包括可以用于电接入电容器和IC芯片内的一般布线的一般布线层的一部分。 烟囱电容器的形成首先在集成电路（“IC”）芯片上形成两个电触头。 在其上形成平面绝缘层，并且电容器至少部分地形成在平面绝缘层内，使得每个板电连接到相应的电接触。

公开(公告)号：US5663101A

公开(公告)日：1997-09-02

申请号：US597747

申请日：1996-02-07

申请人： John Edward Cronin

发明人： John Edward Cronin

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2924/0002

摘要： An improved semiconductor structure is disclosed, including at least one stud-up and an interconnection line connected thereto, wherein the stud-up and interconnection line are formed from a single layer of metal. The structure is prepared by a method in which an insulator region is first provided on a semiconductor substrate, and is then patterned and etched to define at least one opening having a pre-selected depth. Metal is deposited to fill the opening and form the interconnection line, followed by the patterning and formation of a stud-up of desired dimensions within the metal-filled opening. The lower end of the stud-up becomes connected to the interconnection line, and the upper end of the stud-up terminates at or near the upper surface of the insulator region. Other embodiments also include an interconnected stud-down.An endpoint detection technique can be used to precisely control the height of the stud-up and the width of the interconnection line.

摘要翻译： 公开了一种改进的半导体结构，其包括至少一个连接线和与之连接的互连线，其中分离线和互连线由单层金属形成。 该结构通过首先在半导体衬底上提供绝缘体区域的方法制备，然后将其图案化和蚀刻以限定具有预选深度的至少一个开口。 金属沉积以填充开口并形成互连线，随后在金属填充的开口内形成图案并形成所需尺寸的分层。 分支的下端连接到互连线，并且分支的上端终止于或靠近绝缘体区域的上表面。 其他实施例还包括互连的分离。 端点检测技术可以用于精确控制分支的高度和互连线的宽度。

公开(公告)号：US5651857A

公开(公告)日：1997-07-29

申请号：US525269

申请日：1995-09-08

申请人： John Edward Cronin ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

发明人： John Edward Cronin ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/329 ,  H01L21/336 ,  H01L21/3105

CPC分类号： H01L28/40 ,  H01L21/0337 ,  H01L29/66166 ,  H01L29/66659 ,  Y10S438/947

摘要： Improved film spacers for the sidewalls within semiconductor structures are disclosed. The spacers are made of non-conformal, organic materials, such as polyimides, acrylates, methacrylates, and various photoresist compositions. They are formed on the sidewalls by a process which involves the formation of overhang structures. The film spacers may be used for a variety of applications, such as sidewall imaging, control of dopant diffusion in an FET, formation of borderless contacts, and the manufacture of a resistor from an FET.

摘要翻译： 公开了用于半导体结构内的侧壁的改进的膜间隔物。 间隔件由非共形有机材料制成，例如聚酰亚胺，丙烯酸酯，甲基丙烯酸酯和各种光致抗蚀剂组合物。 它们通过涉及形成悬垂结构的方法形成在侧壁上。 膜间隔物可以用于各种应用，例如侧壁成像，FET中掺杂剂扩散的控制，无边界接触的形成以及来自FET的电阻器的制造。

公开(公告)号：US06924555B2

公开(公告)日：2005-08-02

申请号：US10640189

申请日：2003-08-13

申请人： John Edward Cronin ,  Anthony Kendall Stamper

发明人： John Edward Cronin ,  Anthony Kendall Stamper

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/48

CPC分类号： H01L21/76897 ,  H01L21/76804 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76835 ,  H01L21/76837 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device including a contact via having a non-cylindrical bottom portion is disclosed. Also a contact via with non-parallel side walls is disclosed. The contact vias are selectively positioned in the integrated circuit device.

摘要翻译： 公开了一种包括具有非圆柱形底部的接触通孔的集成电路器件。 还公开了一种具有非平行侧壁的接触通孔。 接触通孔选择性地定位在集成电路器件中。

公开(公告)号：US5925924A

公开(公告)日：1999-07-20

申请号：US843177

申请日：1997-04-14

申请人： John Edward Cronin ,  Wayne John Howell ,  Howard Leo Kalter ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

发明人： John Edward Cronin ,  Wayne John Howell ,  Howard Leo Kalter ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

IPC分类号： H01L21/304 ,  H01L21/301 ,  H01L21/78 ,  H01L21/98 ,  H01L25/065 ,  H01L29/06

CPC分类号： H01L25/50 ,  H01L21/78 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/10253 ,  Y10S148/028 ,  Y10S438/977

摘要： Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

摘要翻译： 集成电路（“IC”）芯片具有精确定义的边缘和尺寸。 在晶片处理级别，在切口区域中光刻地蚀刻沟槽，以限定晶片上的IC芯片的边缘。 沟槽填充有绝缘材料，并且晶片上的IC芯片完成了上层布线和金属化。 另外的沟槽被定义为填充的先前形成的沟槽。 将晶片从其底部减薄到填充的沟槽，并且去除其中的绝缘材料以将各个IC芯片与晶片分离。 IC芯片边缘定义的精度有助于将IC芯片更容易地堆叠成堆栈，因为不需要许多堆叠级对准过程。

公开(公告)号：US5882999A

公开(公告)日：1999-03-16

申请号：US692319

申请日：1996-08-05

申请人： Christine Ann Anderson ,  Edward Daniel Buker ,  John Edward Cronin ,  Gloria Jean Kerszykowski ,  David Charles Thomas

发明人： Christine Ann Anderson ,  Edward Daniel Buker ,  John Edward Cronin ,  Gloria Jean Kerszykowski ,  David Charles Thomas

IPC分类号： H01L21/027 ,  H01L21/316 ,  H01L21/768 ,  H01L21/283 ,  H01L21/311

CPC分类号： H01L21/76877 ,  H01L21/76813 ,  H01L2221/1036

摘要： A process for making metal features in an insulator layer in integrated circuits is disclosed. The process involves depositing an antireflective coating layer of a material such as TiN over the insulator layer patterning both the ARC and the insulator with a series of channels or apertures vias and depositing a metal such as tungsten over the ARC and in the channels and apertures. The metal can then be planarized by CMP using the insulator as an etch top.

摘要翻译： 公开了一种用于在集成电路中的绝缘体层中制造金属特征的工艺。 该方法包括在绝缘体层上沉积诸如TiN的材料的抗反射涂层，所述绝缘体层通过一系列通道或孔通孔构图ARC和绝缘体，并且在ARC和通道和孔中沉积诸如钨的金属。 然后可以通过使用绝缘体作为蚀刻顶部的CMP来平坦化金属。

公开(公告)号：US5854141A

公开(公告)日：1998-12-29

申请号：US941447

申请日：1997-09-30

申请人： John Edward Cronin ,  Barbara Jean Luther

发明人： John Edward Cronin ,  Barbara Jean Luther

IPC分类号： H01L21/312 ,  H01L21/314 ,  H01L23/31 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/314 ,  H01L21/312 ,  H01L23/3192 ,  H01L2924/0002 ,  Y10S438/958

摘要： An inorganic seal for encapsulation of an organic layer during passivation of an integrated circuit device and method for making the same is disclosed. The seal creates a structure which forms an inorganic to inorganic passivation seal over Reactive Ion Etched (RIE) edges in an all organic planar back end of the line (BEOL) insulator. The edge seal prevents the delamination of the passivation layer from the integrated circuit device or a metallization ring which may lead to subsequent formation of moisture-filled channels and corrosion of the metal lines of the device and the failure of the integrated circuit.

公开(公告)号：US5818110A

公开(公告)日：1998-10-06

申请号：US755077

申请日：1996-11-22

申请人： John Edward Cronin

发明人： John Edward Cronin

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/5221 ,  H01L21/76877 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S257/923

摘要： An integrated circuit chip wiring structure having crossover and contact capability without an interlock via layer and a method of making the wiring structure all disclosed. The method utilizes a multi-damascene approach, using the standard damascene processing steps to wire the first, then metallization layer, then providing the second, thick metallization layer with first regions for metal wire. A conformal coating is deposited, filling the second regions but not the first regions. When an etch is performed, the layers underlying the second regions are exposed but not those underlying the second regions. Therefore, it is possible to selectively expose the metal lines in the first layer so that electrical connection is made with the metal wire of the second layer in the exposed areas. Electrical isolation is maintained in the narrower, second regions of metal wire.

摘要翻译： 具有不具有互锁通路层的交叉接触能力的集成电路芯片布线结构和全部公开了布线结构的方法。 该方法使用多镶嵌方法，使用标准镶嵌处理步骤来对第一层，然后金属化层进行接线，然后为第二厚金属化层提供金属线的第一区域。 沉积保形涂层，填充第二区域而不是第一区域。 当进行蚀刻时，第二区域下面的层被暴露，但不暴露第二区域的层。 因此，可以选择性地暴露第一层中的金属线，使得在暴露区域中与第二层的金属线进行电连接。 在金属丝的较窄的第二区域中保持电隔离。

公开(公告)号：US5719438A

公开(公告)日：1998-02-17

申请号：US469090

申请日：1995-06-06

申请人： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  John Edward Cronin ,  Wayne John Howell ,  James Marc Leas ,  David Jacob Perlman

发明人： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  John Edward Cronin ,  Wayne John Howell ,  James Marc Leas ,  David Jacob Perlman

IPC分类号： H01L21/98 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L23/02 ,  H01L23/04

CPC分类号： H01L25/50 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/30107

摘要： A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.