公开(公告)号：US07439581B2

公开(公告)日：2008-10-21

申请号：US11704364

申请日：2007-02-09

申请人： Seong-Goo Kim ,  Kang-Yoon Lee ,  Yun-Gi Kim ,  Bong-Soo Kim

发明人： Seong-Goo Kim ,  Kang-Yoon Lee ,  Yun-Gi Kim ,  Bong-Soo Kim

IPC分类号： H01L29/76

CPC分类号： H01L23/485 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material layer having first and second regions may be prepared. A trench may be formed in a selected portion of the first region. Transistors or semiconductor integrated circuit interconnections may be in the first and second regions, respectively. One of the transistors or the semiconductor integrated circuit interconnections may be formed in the trench. The transistors or the semiconductor integrated circuit interconnections may be electrically insulated from each other.

公开(公告)号：US20080179647A1

公开(公告)日：2008-07-31

申请号：US11964146

申请日：2007-12-26

申请人： Hyeoung-won Seo ,  Dong-hyun Kim ,  Kang-yoon Lee ,  Seong-goo Kim

发明人： Hyeoung-won Seo ,  Dong-hyun Kim ,  Kang-yoon Lee ,  Seong-goo Kim

IPC分类号： H01L27/108 ,  H01L21/8239

CPC分类号： H01L27/10885 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876

摘要： A semiconductor device comprising a barrier insulating layer and a related method of fabrication is disclosed. The semiconductor device semiconductor substrate includes a plurality of active regions, wherein active regions are defined by a device isolation layer and are disposed along a first direction; a plurality of bit line electrodes connected to the active regions, wherein each of the bit line electrodes extends along a second direction; and a plurality of first barrier insulating layers. Each of the first barrier insulating layers extends along a third direction, at least one of the first barrier insulating layers is disposed on a corresponding first portion of the device isolation layer disposed between two of the active regions, the two of the active regions are adjacent along the first direction, and the first direction and the second direction differ from one another.

摘要翻译： 公开了一种包括阻挡绝缘层和相关制造方法的半导体器件。 半导体器件半导体衬底包括多个有源区，其中有源区由器件隔离层限定，并沿着第一方向设置; 连接到有源区的多个位线电极，其中每个位线电极沿着第二方向延伸; 以及多个第一阻挡绝缘层。 每个第一阻挡绝缘层沿着第三方向延伸，至少一个第一阻挡绝缘层设置在设置在两个有源区之间的器件隔离层的对应的第一部分上，两个有源区相邻 沿第一方向，第一方向和第二方向彼此不同。

公开(公告)号：US07387931B2

公开(公告)日：2008-06-17

申请号：US11546581

申请日：2006-10-11

申请人： Hyeoung-won Seo ,  Jae-man Yoon ,  Kang-yoon Lee ,  Dong-gun Park ,  Bong-soo Kim ,  Seong-goo Kim

发明人： Hyeoung-won Seo ,  Jae-man Yoon ,  Kang-yoon Lee ,  Dong-gun Park ,  Bong-soo Kim ,  Seong-goo Kim

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/7827

摘要： In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.

摘要翻译： 在具有其主体连接到基板的垂直沟道晶体管的半导体存储器件及其制造方法中，半导体存储器件包括：半导体衬底，其包括彼此间隔布置的多个柱，并且每个 支柱包括主体部分和从主体部分延伸并彼此间隔开的一对柱部分。 形成围绕每个支柱部分的栅电极。 位于所述主体部分上的位线穿过所述第一支柱中的所述第一支柱的一对支柱之间的区域，所述第一支柱布置成沿第一方向延伸。 字线布置在位线之外，布置成沿与第一方向相交的第二方向延伸，并且被配置为接触栅电极的侧表面。 第一掺杂区域形成在柱的每个柱部分的上表面中。 第二掺杂区形成在柱的主体部分上并与电位线连接。 存储节点电极与第一掺杂区域电连接并设置在每个柱部分上。

公开(公告)号：US20070284647A1

公开(公告)日：2007-12-13

申请号：US11705109

申请日：2007-02-12

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7834

摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

摘要翻译： 半导体器件可以包括具有电池有源区的衬底。 可以在电池活性区域中形成电池栅电极。 单元栅极覆盖层可以形成在单元栅电极上。 至少两个电池外延层可以形成在电池有源区上。 至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。 电池杂质区域可以设置在电池活性区域中。 电池杂质区域可以对应于至少两个电池外延层中的相应一个。

公开(公告)号：US20070015362A1

公开(公告)日：2007-01-18

申请号：US11457726

申请日：2006-07-14

申请人： Cheol-Ju YUN ,  Kang-Yoon LEE ,  In-Ho NAM

发明人： Cheol-Ju YUN ,  Kang-Yoon LEE ,  In-Ho NAM

IPC分类号： H01L21/302

CPC分类号： H01L21/76885 ,  H01L21/76834 ,  H01L27/10855

摘要： Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an etch stop layer disposed on the conductive pad and the interlayer insulating layer; and storage nodes penetrating the etch stop layer and disposed on the conductive pad. A penetration path of wet etchant is completely blocked during the wet etch process that removes the mold oxide layer. Therefore, inadvertent etching of the insulating layer due to penetration of wet etchant is prevented, resulting in a stronger, more stable, storage node structure.

摘要翻译： 具有存储节点的半导体器件的实施例包括设置在半导体衬底上的层间绝缘层; 布置在所述层间绝缘层中以与所述基板的预定部分接触的导电焊盘，所述导电焊盘的上部突出于所述层间绝缘层的上方; 设置在所述导电焊盘和所述层间绝缘层上的蚀刻停止层; 并且存储节点穿透蚀刻停止层并且设置在导电焊盘上。 在湿法蚀刻工艺期间，湿蚀刻剂的穿透路径被完全阻挡，从而去除了模具氧化物层。 因此，防止了由于潮湿蚀刻剂的渗透而导致的绝缘层的无意蚀刻，导致更坚固，更稳定的存储节点结构。

公开(公告)号：US06963620B2

公开(公告)日：2005-11-08

申请号：US10284342

申请日：2002-10-31

申请人： Kang-Yoon Lee ,  Eunseok Song ,  Jeong Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Kang-Yoon Lee ,  Eunseok Song ,  Jeong Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H03C3/09 ,  H04L27/04 ,  H03D3/24 ,  H04L27/12 ,  H04L27/20

CPC分类号： H03C3/0966 ,  H03C3/0933

摘要： A translational-loop transmitter generates RF signals using at most one phase-locked-loop (PLL) circuit. In one embodiment, a single PLL generates two local oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type of modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under these conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is used to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. In still other embodiments, a transmitter signal is generated without using any phase-locked-loop circuits. This is accomplished by generating an intermediate frequency signal using a crystal oscillator, and then using a frequency divider in a feedback loop to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. By minimizing the number of phase-locked-loop circuits in the transmitter, the size, cost, and power requirements of mobile handsets may be significantly reduced.

摘要翻译： 平移环路发射器使用至多一个锁相环（PLL）电路产生RF信号。 在一个实施例中，单个PLL产生两个本地振荡信号。 第一振荡信号与基带信号混合以产生中频信号。 第二振荡信号被输入到平移回路中，以将压控振荡器调整到期望的载波频率。 为了执行这种类型的调制，本地振荡信号的频率被设置为使得它们相对于载波频率彼此谐波相关。 其他实施例仅产生一个振荡信号。 在这些条件下，使用振荡信号产生中频信号，并且使用平移环路中的分频器产生用于将压控振荡器调节到载波频率的控制信号。 在其他实施例中，产生发射机信号而不使用任何锁相环电路。 这是通过使用晶体振荡器产生中频信号，然后在反馈环路中使用分频器来产生用于将压控振荡器调节到载波频率的控制信号来实现的。 通过最小化发射机中的锁相环电路的数量，移动手机的尺寸，成本和功率要求可能会大大降低。

公开(公告)号：US5900659A

公开(公告)日：1999-05-04

申请号：US987281

申请日：1997-12-09

申请人： Kang-yoon Lee

发明人： Kang-yoon Lee

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/743 ,  H01L27/10808 ,  Y10S257/908

摘要： A buried bit line DRAM cell includes an active region having a protruding tap, formed in a semiconductor substrate. A device isolation region is formed in the substrate, outside the active region. A bit line laterally contacts the tap and is buried in the device isolation region. Accordingly, photolithography steps for forming a device isolation film twice and for forming a bit line contact can be omitted, thereby obtaining process simplicity and wider process margins.

摘要翻译： 掩埋位线DRAM单元包括形成在半导体衬底中的具有突出抽头的有源区。 器件隔离区形成在衬底中，在有源区之外。 位线横向接触抽头并被埋在设备隔离区域中。 因此，可以省略用于形成器件隔离膜两次并形成位线接触的光刻步骤，从而获得工艺简单性和更宽的工艺裕度。

公开(公告)号：US08482045B2

公开(公告)日：2013-07-09

申请号：US13549648

申请日：2012-07-16

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，从而容易地制造高度集成的半导体存储器件。

公开(公告)号：US20130147531A1

公开(公告)日：2013-06-13

申请号：US13817816

申请日：2011-08-19

申请人： Kang-Yoon Lee ,  Young-Gun Pu ,  An-Soo Park ,  Joon-Sung Park ,  Jae-Sup Lee

发明人： Kang-Yoon Lee ,  Young-Gun Pu ,  An-Soo Park ,  Joon-Sung Park ,  Jae-Sup Lee

IPC分类号： H03L7/089

CPC分类号： H03L7/089 ,  H03L7/085 ,  H03L7/18 ,  H03L2207/50

摘要： A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval.

摘要翻译： 提供了无线通信系统中的数字锁相环（PLL）。 PLL包括数字控制振荡器（DCO），分频器，相位频率检测器（PFD），时间到数字转换器（TDC），延迟比较器和电平定标器。 DCO根据输入数字调谐字（DTW）产生频率信号。 分频器以整数比除成频率信号。 PFD产生表示分频信号和参考信号之间的相位差的信号。 TDC使用表示相位差的信号来测量相位差的时间间隔。 延迟比较器计算上升沿与TDC测量值相符的时间间隔。 级别缩放器生成使用表示时间间隔的数字代码来操作DCO的DTW。

公开(公告)号：US08174065B2

公开(公告)日：2012-05-08

申请号：US12840599

申请日：2010-07-21

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L29/66

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。