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    Resistive Memory Structure with Buffer Layer
    11.
    发明申请
    Resistive Memory Structure with Buffer Layer 有权
    具有缓冲层的电阻式存储器结构

    公开(公告)号：US20100276658A1

    公开(公告)日：2010-11-04

    申请号：US12836304

    申请日：2010-07-14

    Applicant: Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    Inventor： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC: H01L45/00

    CPC classification number: H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633 ,  Y10S438/90

    Abstract: A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

    Abstract translation: 存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。 记忆元件包括一种或多种金属氧化合物。 缓冲层包括氧化物和氮化物中的至少一种。 另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。 记忆体包括一种或多种金属氧化合物。 制造存储器件的方法的一个例子包括形成第一和第二电极。 形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

    NAND FLASH BIASING OPERATION
    13.
    发明申请
    NAND FLASH BIASING OPERATION 有权
    NAND闪存偏移操作

    公开(公告)号：US20130343130A1

    公开(公告)日：2013-12-26

    申请号：US13710992

    申请日：2012-12-11

    Applicant: TI-WEN CHEN ,  HANG-TING LUE ,  SHUO-NAN HUNG ,  SHIH-LIN HUANG ,  CHIH-CHANG HSIEH ,  KUO-PIN CHANG

    Inventor： TI-WEN CHEN ,  HANG-TING LUE ,  SHUO-NAN HUNG ,  SHIH-LIN HUANG ,  CHIH-CHANG HSIEH ,  KUO-PIN CHANG

    IPC: G11C16/06

    CPC classification number: G11C16/26 ,  G11C5/146 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157

    Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.

    Abstract translation: 电荷存储存储器配置在NAND阵列中，并且包括经由串选择开关耦合到位线的NAND串并且包括字线。 控制器被配置为产生用于对NAND阵列的所选单元执行操作的偏置。 该偏置包括在字符串选择开关闭合时对位线进行充电，例如不会将这种位线充电引起的噪声引入串中。 在耦合到所选字线的NAND串中的存储器单元的两侧的存储单元中的半导体主体区域被耦合到参考电压，使得它们被预充电，而阵列中的字符串的字线 在操作期间转变为各种电压。

    Memory and Method of Fabricating the Same
    14.
    发明申请
    Memory and Method of Fabricating the Same 有权
    内存及其制作方法

    公开(公告)号：US20110089393A1

    公开(公告)日：2011-04-21

    申请号：US12581219

    申请日：2009-10-19

    Applicant: Kuo-Pin Chang ,  Erh-Kun Lai

    Inventor： Kuo-Pin Chang ,  Erh-Kun Lai

    IPC: H01L45/00 ,  H01L29/12 ,  H01L21/34

    CPC classification number: G11C11/5685 ,  G11C13/0007 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

    Abstract: A memory, comprising a metal portion, a first metal layer and second metal oxide layer is provided. The first metal oxide layer is on the metal element, and the first metal oxide layer includes N resistance levels. The second metal oxide layer is on the first metal oxide layer, and the second metal oxide layer includes M resistance levels. The memory has X resistance levels and X is less than the summation of M and N, for minimizing a programming disturbance.

    Abstract translation: 提供了包括金属部分，第一金属层和第二金属氧化物层的存储器。 第一金属氧化物层在金属元件上，第一金属氧化物层包括N电阻水平。 第二金属氧化物层在第一金属氧化物层上，第二金属氧化物层包括M电阻水平。 存储器具有X电阻电平，并且X小于M和N的总和，以最小化编程干扰。

    Transistor having an adjustable gate resistance and semiconductor device comprising the same
    15.
    发明授权
    Transistor having an adjustable gate resistance and semiconductor device comprising the same 有权
    具有可调节栅极电阻的晶体管和包括其的半导体器件

    公开(公告)号：US08675381B2

    公开(公告)日：2014-03-18

    申请号：US12839842

    申请日：2010-07-20

    Applicant: Hang-Ting Lue ,  Kuo-Pin Chang

    Inventor： Hang-Ting Lue ,  Kuo-Pin Chang

    IPC: G11C5/06

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C11/5692 ,  G11C16/0483 ,  G11C17/165 ,  G11C2013/0071 ,  G11C2213/15 ,  G11C2213/53 ,  G11C2213/75

    Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.

    Abstract translation: 存储器件包括每个能够存储多个数据位的存储器单元的阵列。 存储单元被布置在连接到公共源极线的存储器串中。 每个存储单元包括与电阻串联连接的可编程晶体管。 晶体管包括可在多个不同电阻值之间切换的栅极电介质。 晶体管的阈值电压根据栅极电介质的电阻值而变化。 因此，存储器单元的存储器状态可以与晶体管的电介质层的相应电阻值相关联。

    Clip assembly for a pacifier
    19.
    发明授权
    Clip assembly for a pacifier 失效
    夹子组装为奶嘴

    公开(公告)号：US06243921B1

    公开(公告)日：2001-06-12

    申请号：US09450418

    申请日：1999-11-30

    Applicant: Kuo Pin Chang

    Inventor： Kuo Pin Chang

    IPC: A61J1700

    CPC classification number: A61J17/00 ,  A61J17/001 ,  Y10T24/1397

    Abstract: A clip assembly for a pacifier includes a fastener, a cover having one side fixedly engaged with the fastener and another side provided with a resilient projection, a circular container having radial outlet and an axle at a central portion thereof, a reel fitted within the circular container and having a center hole receiving the axle, the reel having a circular recess provided with a plurality of radial teeth on an inner circumference thereof and two positioning members adjacent to the radial teeth, a spiral spring fitted within the circular recess of the reel and having an inner end fixedly secured to the axle and an outer end fixedly connected to the positioning members, a circular plate mounted in the circular recess to prevent the spiral spring from getting out of the circular recess, a cord having an end fixedly secured to the circumferential groove, and a retainer fixedly connected to another end of the cord and having a fastening member and a linking chain having a plurality of ball-shaped elements engageable with the fastening member, whereby it is only necessary to pull the pacifier and push the switch to keep the cord at a fixed position when a child wants to suck the pacifier, and open the switch to release the cord to enable the spiral spring to rewind the cord and pull back the pacifier when the child spits out the pacifier, thereby preventing the pacifier from being made dirty.

    Abstract translation: 用于奶嘴的夹子组件包括紧固件，具有与紧固件固定接合的一侧的盖，设置有弹性突起的另一侧，具有径向出口的圆形容器和在其中心部分处的轴;安装在圆形 容器并且具有容纳轴的中心孔，所述卷轴具有在其内周上设置有多个径向齿的圆形凹槽和与径向齿相邻的两个定位构件，装配在卷轴的圆形凹部内的螺旋弹簧， 具有固定在轴上的内端和固定地连接到定位构件的外端;安装在圆形凹槽中的圆形板，以防止螺旋弹簧脱离圆形凹槽;绳索，其一端固定地固定到 固定连接到绳索的另一端并具有紧固构件和具有多个的连接链的保持器 球形元件可与紧固件接合，因此只有当孩子想要吸吮奶嘴时才需要拉动奶嘴并推动开关以将绳索保持在固定位置，并打开开关以松开绳子以使能 当孩子吐出奶嘴时螺旋弹簧回绕绳索并拉回奶嘴，从而防止奶嘴变脏。

    PROGRAMMING TECHNIQUE FOR REDUCING PROGRAM DISTURB IN STACKED MEMORY STRUCTURES
    20.
    发明申请
    PROGRAMMING TECHNIQUE FOR REDUCING PROGRAM DISTURB IN STACKED MEMORY STRUCTURES 审中-公开
    用于减少堆叠存储器结构中的程序干扰的编程技术

    公开(公告)号：US20140198576A1

    公开(公告)日：2014-07-17

    申请号：US13827475

    申请日：2013-03-14

    Applicant: Shuo-Nan Hung ,  HANG-TING LUE ,  TI-WEN CHEN ,  SHIH-LIN HUANG ,  KUO-PIN CHANG ,  CHIH-CHANG HSIEH ,  CHUN-HSIUNG HUNG

    Inventor： Shuo-Nan Hung ,  HANG-TING LUE ,  TI-WEN CHEN ,  SHIH-LIN HUANG ,  KUO-PIN CHANG ,  CHIH-CHANG HSIEH ,  CHUN-HSIUNG HUNG

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14 ,  H01L27/11551 ,  H01L27/11578

    Abstract: A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set.

    Abstract translation: 描述用于对具有多层存储器单元的堆叠存储器结构进行编程的编程偏置技术。 该技术包括响应于程序指令的控制器电路，以在特定多位地址的单元堆栈中的目标单元格中​​编程数据。 电路被配置为使用单元格堆栈中的单元格分配给多个单元组，并且迭代地执行依次选择多个集合中的每一个的设置程序操作。 每个迭代包括对多个组中的其他单元中的所有单元施加抑制电压。 此外，每组层包括一个或两个子集，并且存在至少两个层，其中一组将每个子集分隔开。

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