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    Circuit and method for temperature tracing of devices including an element of chalcogenic material, in particular phase change memory devices
    11.
    发明申请
    Circuit and method for temperature tracing of devices including an element of chalcogenic material, in particular phase change memory devices 有权
    用于包括硫属元素元素的装置的温度追踪的电路和方法，特别是相变存储器件

    公开(公告)号：US20040151023A1

    公开(公告)日：2004-08-05

    申请号：US10715883

    申请日：2003-11-18

    Applicant: STMicroelectronics S.r.I. ,  OVONYX Inc.

    Inventor： Osama Khouri ,  Ferdinando Bedeschi ,  Claudio Resta

    IPC: G11C011/00

    CPC classification number: G11C7/04 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2029/5002 ,  G11C2213/79

    Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor of chalcogenic material furnishing an electrical quantity that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

    Abstract translation: 相变存储器包括具有与相变存储元件相同定律的具有温度的电阻变化的温度传感器。 该温度传感器是由一个硫化物材料的电阻器形成的，它提供一个再现相变存储器单元电阻和温度之间的关系的电量; 对电量进行处理，以便产生写入和读取存储单元所需的参考量。 硫属电阻器具有与存储器单元相同的结构，并且精确地编程，优选地处于复位状态。

    Array of cells including a selection bipolar transistor and fabrication method thereof
    12.
    发明申请
    Array of cells including a selection bipolar transistor and fabrication method thereof 有权
    包括选择双极晶体管的单元阵列及其制造方法

    公开(公告)号：US20040150093A1

    公开(公告)日：2004-08-05

    申请号：US10680727

    申请日：2003-10-07

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

    IPC: H01L023/48

    CPC classification number: H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

    Abstract: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

    Abstract translation: 单元阵列由多个单元形成，每个单元包括选择双极晶体管和存储组件。 电池阵列形成在包括P型共用集电极区域的主体中; 多个N型基极区，覆盖在公共集电极区域上; 在基区中形成多个P型发射极区; 以及形成在所述基极区域中的多个N型基极接触区域和比所述基极区域更高的掺杂水平的基极接触区域，其中每个基极区域由至少两个相邻的双极晶体管共享。

    Contact structure, phase change memory cell, and manufacturing method thereof with elimination of double contacts
    13.
    发明申请
    Contact structure, phase change memory cell, and manufacturing method thereof with elimination of double contacts 有权
    接触结构，相变存储单元及其消除双触点的制造方法

    公开(公告)号：US20030214856A1

    公开(公告)日：2003-11-20

    申请号：US10372639

    申请日：2003-02-20

    Applicant: STMicroelectronics S. r. I. ,  OVONYX Inc.

    Inventor： Fabio Pellizzer ,  Agostino Pirovano

    IPC: G11C007/00

    CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: The phase change memory cell is formed by a resistive element and by a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction which is transverse to said first direction. The first and second thin portions are in direct electrical contact and define a contact area having sublithographic extent. The second thin portion is formed in a slit of sublithographic dimensions. According to a first solution, oxide spacer portions are formed in a lithographic opening, delimited by a mold layer. According to a different solution, a sacrificial region is formed on top of a mold layer and is used for forming the sublithographic slit in the mold layer.

    Abstract translation: 相变存储单元由电阻元件和相变材料的存储区形成。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区具有第二薄部，所述第二薄部在与所述第一方向横切的第二方向上具有第二亚光刻尺寸。 第一和第二薄部分是直接电接触并限定具有亚光刻范围的接触区域。 第二薄部分形成在亚光刻尺寸的狭缝中。 根据第一种解决方案，氧化物间隔物部分形成在由模具层限定的光刻开口中。 根据不同的解决方案，牺牲区域形成在模具层的顶部上，并用于在模具层中形成亚光刻缝。

    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step
    15.
    发明申请
    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step 有权
    用于制造存储器件的方法，特别是包括硅化步骤的相变存储器

    公开(公告)号：US20040214415A1

    公开(公告)日：2004-10-28

    申请号：US10758289

    申请日：2004-01-15

    Applicant: STMicroelectronics S.r.I. ,  OVONYX Inc.

    Inventor： Fabio Pellizzer ,  Roberto Bez ,  Marina Tosi

    IPC: H01L021/28

    CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the array portion; the gate electrode and the active areas of the circuitry portion are silicided and the first silicide protection mask is removed. The first silicide protection mask (is of polysilicon and is formed simultaneously with the gate electrode. A second silicide protection mask of dielectric material covering the first silicide protection mask is formed before silicidation of the gate electrode. The second silicide protection mask is formed simultaneously with spacers formed laterally to the gate electrode.

    Abstract translation: 一种绝缘区域至少在半导体本体的阵列部分周围形成在主体中的工艺; 半导体材料的栅电极形成在半导体本体的电路部分的顶部; 在阵列部分的顶部形成第一硅化物保护掩模; 栅电极和电路部分的有源区被硅化，并且去除第一硅化物保护掩模。 第一硅化物保护掩模（多晶硅，并与栅电极同时形成）在栅极电极硅化之前形成覆盖第一硅化物保护掩模的第二硅化物保护掩模，第二硅化物保护掩膜与 间隔件横向形成到栅电极。

    Process for manufacturing an array of cells including selection bipolar junction transistors
    17.
    发明申请
    Process for manufacturing an array of cells including selection bipolar junction transistors 有权
    用于制造包括选择双极结型晶体管的单元阵列的工艺

    公开(公告)号：US20040130000A1

    公开(公告)日：2004-07-08

    申请号：US10680721

    申请日：2003-10-07

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Gastaldi ,  Loris Vendrame ,  Augusto Benvenuti ,  Tyler Lowrey

    IPC: H01L027/082

    CPC classification number: H01L29/685 ,  H01L27/101 ,  H01L27/24

    Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component having a terminal connected to a respective second conduction region.

    Abstract translation: 一种用于制造单元阵列的方法，包括：在第一导电类型的半导体材料的主体中注入第一导电类型的共同导电区域; 在体内在公共导电区域上形成第二导电类型和第一掺杂水平的多个有源区域区域; 在所述主体的顶部上形成具有第一和第二开口的绝缘层; 通过第一导电类型的掺杂剂将有源区域的第一部分注入第一开口，从而在有源区域中形成第一导电类型的第二导电区域; 通过第二导电类型的掺杂剂将有源区域的第二部分注入第二开口，由此形成高于第一掺杂级的第二导电类型和第二掺杂级的控制接触区; 在主体的顶部上形成多个存储部件，每个存储部件具有连接到相应的第二传导区域的端子。

    Architecture of a phase-change nonvolatile memory array
    18.
    发明申请
    Architecture of a phase-change nonvolatile memory array 有权
    相变非易失性存储器阵列的体系结构

    公开(公告)号：US20030185047A1

    公开(公告)日：2003-10-02

    申请号：US10319439

    申请日：2002-12-12

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Osama Khouri ,  Ferdinando Bedeschi ,  Giorgio Bosisio ,  Fabio Pellizzer

    IPC: G11C011/00

    CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: The phase-change nonvolatile memory array is formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.

    Abstract translation: 相变非易失性存储器阵列由在彼此正交的第一和第二方向上延伸的多个存储单元形成。 多个列选择线平行于第一方向延伸。 多个字选择线平行于第二方向延伸。 每个存储单元包括PCM存储元件和选择晶体管。 选择晶体管的第一端子连接到PCM存储元件的第一端子，并且选择晶体管的控制端子连接到相应的字选择线。 PCM存储元件的第二端子连接到相应的列选择线，并且在读取和编程存储器单元的同时，选择晶体管的第二端子连接到参考电位区域。

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