公开(公告)号：US20110298000A1

公开(公告)日：2011-12-08

申请号：US13154337

申请日：2011-06-06

Applicant: Tsang-Yu LIU ,  Yu-Lin YEN ,  Chuan-Jin SHIU ,  Po-Shen LIN

Inventor： Tsang-Yu LIU ,  Yu-Lin YEN ,  Chuan-Jin SHIU ,  Po-Shen LIN

IPC: H01L33/52 ,  H01L31/0203

CPC classification number: H01L27/14623 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L33/44 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01021 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

Abstract: According to an embodiment of the invention, a chip package is provided, which includes: a substrate having a first surface and a second surface; an optical device between the first surface and the second surface of the substrate; a protection layer formed on the second surface of the substrate, wherein the protection layer has at least an opening; at least a conducting bump formed in the opening of the protection layer and electrically connected to the optical device; and a light shielding layer formed on the protection layer, wherein the light shielding layer is further extended onto a sidewall of the opening of the protection layer.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 在所述基板的所述第一表面和所述第二表面之间的光学装置; 形成在所述基板的第二表面上的保护层，其中所述保护层具有至少一个开口; 至少形成在所述保护层的开口中并电连接到所述光学装置的导电凸起; 以及形成在所述保护层上的遮光层，其中所述遮光层进一步延伸到所述保护层的开口的侧壁上。

公开(公告)号：US08890191B2

公开(公告)日：2014-11-18

申请号：US13536628

申请日：2012-06-28

Applicant: Chuan-Jin Shiu ,  Po-Shen Lin ,  Yi-Ming Chang

Inventor： Chuan-Jin Shiu ,  Po-Shen Lin ,  Yi-Ming Chang

IPC: H01L33/00 ,  H01L21/00 ,  H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/1463 ,  H01L2224/13 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer; and a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate.

Abstract translation: 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 形成在所述基板中的光电子器件; 设置在所述基板上的导电层，其中所述导电层电连接到所述光电子器件; 设置在所述基板和所述导电层之间的绝缘层; 遮光层，其设置在所述基板的所述第二表面上并与所述导电层直接接触，其中所述遮光层具有大于约80％的遮光率并且具有暴露所述导电层的至少一个开口; 以及布置在所述遮光层的开口中以与所述导电层电接触的导电凸块，其中所述遮光层和所述导电凸起部分都基本上完全覆盖所述基板的第二表面。

公开(公告)号：US08854288B2

公开(公告)日：2014-10-07

申请号：US13380892

申请日：2011-09-19

Applicant: Po-shen Lin ,  Xiaoping Tan ,  Jianyong Fu

Inventor： Po-shen Lin ,  Xiaoping Tan ,  Jianyong Fu

IPC: G09G3/36

CPC classification number: G09G3/36 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2330/045

Abstract: A tangent angle circuit is connected to a plurality of scan line driving circuits and comprises: a charging module integrated on a control board to receive input of a direct current (DC) driving voltage and output a cut-in voltage to charge the scan line driving circuits; and a plurality of discharging modules integrated on the scan line driving circuits respectively to control the corresponding scan line driving circuits to discharge. In the present invention, by distributing the discharging modules on each of the scan line driving circuits respectively, the burden of load discharged charges on the discharging modules is reduced to avoid occurrence of an overhigh temperature; and the discharging modules are spatially separated, which is further favorable for reducing the temperature, releasing the space of the control board and reducing the area of the control board.

Abstract translation: 切线角电路连接到多条扫描线驱动电路，包括：集成在控制板上的充电模块，用于接收直流（DC）驱动电压的输入，并输出一个插入电压以对扫描线驱动进行充电 电路; 以及分别集成在扫描线驱动电路上的多个放电模块，以控制相应的扫描线驱动电路放电。 在本发明中，通过分别在每条扫描线驱动电路上分配放电模块，降低放电模块上的负载放电电荷的负担，以避免发生超高温度; 并且放电模块在空间上分离，这进一步有利于降低温度，释放控制板的空间并减小控制板的面积。

公开(公告)号：US08779557B2

公开(公告)日：2014-07-15

申请号：US13476748

申请日：2012-05-21

Applicant: Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chia-Ming Cheng ,  Po-Shen Lin

Inventor： Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chia-Ming Cheng ,  Po-Shen Lin

IPC: H01L21/78 ,  H01L21/68 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/682 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a substrate, wherein the substrate is diced from a wafer; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a material layer formed on the insulating layer, wherein the material layer has a recognition mark, and the recognition mark shows position information of the substrate in the wafer before the substrate is diced from the wafer.

Abstract translation: 本发明的实施例提供了一种芯片封装，其包括：衬底，其中所述衬底从晶片切割; 形成在所述基板中的器件区域; 导电层，其设置在所述基板上并电连接到所述器件区域; 设置在所述基板和所述导电层之间的绝缘层; 以及形成在所述绝缘层上的材料层，其中所述材料层具有识别标记，并且所述识别标记在从所述晶片切割所述基板之前，示出所述晶片中的所述基板的位置信息。

公开(公告)号：US08760882B2

公开(公告)日：2014-06-24

申请号：US13300392

申请日：2011-11-18

Applicant: Yi-Ming Chang ,  I-Min Lin ,  Po-Shen Lin

Inventor： Yi-Ming Chang ,  I-Min Lin ,  Po-Shen Lin

IPC: H05K7/10

CPC classification number: H05K3/06 ,  H01L21/4853 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/14 ,  H05K3/244 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/00

Abstract: A wiring structure for improving a crown-like defect and a fabrication method thereof are provided. The method includes the following steps. A substrate, on which a seed layer and a patterned photoresist layer with an opening are formed, is provided. A copper layer, having a bottom covering the seed layer, is formed in the opening. A barrier layer covering at least one top portion of the copper layer is formed on the copper layer. An oxidation potential of the barrier layer is greater than that of the copper layer. The patterned photoresist layer is removed to perform an etching process, wherein the copper layer and a portion of the seed layer exposed are etched to form a wiring layer. An immersion process is performed to form an anti-oxidation layer comprehensively on exposed surfaces of the barrier layer and the wiring layer.

Abstract translation: 提供了一种用于改善冠状缺陷的布线结构及其制造方法。 该方法包括以下步骤。 提供了其上形成有种子层和具有开口的图案化光致抗蚀剂层的衬底。 在开口中形成有覆盖种子层的底部的铜层。 覆盖铜层的至少一个顶部的阻挡层形成在铜层上。 阻挡层的氧化电位大于铜层的氧化电位。 去除图案化的光致抗蚀剂层以进行蚀刻工艺，其中铜层和暴露的种子层的一部分被蚀刻以形成布线层。 进行浸渍处理以在阻挡层和布线层的暴露表面上综合地形成抗氧化层。

公开(公告)号：US20130120344A1

公开(公告)日：2013-05-16

申请号：US13380043

申请日：2011-11-18

Applicant: Liang-chan Liao ,  Po-shen Lin ,  Dongsheng Guo

Inventor： Liang-chan Liao ,  Po-shen Lin ,  Dongsheng Guo

IPC: G09G3/36 ,  G09G5/00

CPC classification number: G06F3/041 ,  G09G3/3688 ,  G09G5/00 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/06

Abstract: An output compensation circuit and an output compensation method for an LCD data drive IC as well as an LCD comprising the same are disclosed. The output compensation circuit comprises a data drive IC, a plurality of first switch units and a plurality of delay control units. A plurality of output channels of the data drive IC each are connected with a corresponding row of pixel electrodes on a glass substrate via a data line respectively to output a charging signal. Each of the first switch units control the corresponding output channel according to a delay control signal generated by the corresponding delay control unit. Each of the delay control units is configured to generate the delay control signal-used to control the first switch unit to be turned on after a predetermined delay so that the charging time is the same for all the pixel electrodes.

Abstract translation: 公开了一种用于LCD数据驱动IC的输出补偿电路和输出补偿方法以及包括其的LCD。 输出补偿电路包括数据驱动IC，多个第一开关单元和多个延迟控制单元。 数据驱动IC的多个输出通道分别经由数据线与玻璃基板上的相应行像素电极分别连接以输出充电信号。 每个第一开关单元根据由相应的延迟控制单元产生的延迟控制信号来控制对应的输出通道。 每个延迟控制单元被配置为产生用于在预定延迟之后控制要接通的第一开关单元的延迟控制信号，使得对于所有像素电极的充电时间相同。

公开(公告)号：US20130114226A1

公开(公告)日：2013-05-09

申请号：US13378566

申请日：2011-11-08

Applicant: Liang-Chan Liao ,  Po-Shen Lin ,  Yuxin Bi

Inventor： Liang-Chan Liao ,  Po-Shen Lin ,  Yuxin Bi

IPC: H05K7/06

CPC classification number: H01L23/4985 ,  G02F1/13 ,  H01L24/97 ,  H01L2924/14 ,  H01L2924/00

Abstract: The invention discloses a COF packaging unit and a COF packaging tape. The COF packaging unit comprises COF baseband(s), IC Die(s) packaged on the COF baseband(s), and input end wires and output end wires connected with the IC Die(s); the input end wires and the output end wires are respectively provided with input terminals and output terminals at two edges of the COF baseband. In the invention, because the input terminals and the output terminals are pitched along the edges of the COF baseband, the length of the single COF packaging unit is set in accordance with the pitching requirement of the input end wires and the output end wires, so that the COF baseband can have sufficient area for wiring, to adapt to the requirement of large LCD panels. Thus, resources are reasonably integrated and used, equipment utilization rate is increased, material purchasing cost is saved, and economic benefits are increased.

Abstract translation: 本发明公开了一种COF包装单元和COF包装带。 COF封装单元包括COF基带，封装在COF基带上的IC芯片，以及与IC芯片连接的输入端线和输出端线; 输入端线和输出端线分别在COF基带的两个边缘处设置有输入端子和输出端子。 在本发明中，由于输入端子和输出端子沿着COF基带的边缘倾斜，所以单个COF封装单元的长度根据输入端线和输出端线的俯仰要求而设定，因此 COF基带可以有足够的布线面积，以适应大型液晶面板的需求。 资源合理整合利用，设备利用率提高，物资采购成本节省，经济效益提高。

公开(公告)号：US20130057461A1

公开(公告)日：2013-03-07

申请号：US13380892

申请日：2011-09-19

Applicant: Po-shen Lin ,  Xiaoping Tan ,  Jianyong Fu

Inventor： Po-shen Lin ,  Xiaoping Tan ,  Jianyong Fu

IPC: G09G3/36

CPC classification number: G09G3/36 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2330/045

Abstract: A tangent angle circuit is connected to a plurality of scan line driving circuits and comprises: a charging module integrated on a control board to receive input of a direct current (DC) driving voltage and output a cut-in voltage to charge the scan line driving circuits; and a plurality of discharging modules integrated on the scan line driving circuits respectively to control the corresponding scan line driving circuits to discharge. In the present invention, by distributing the discharging modules on each of the scan line driving circuits respectively, the burden of load discharged charges on the discharging modules is reduced to avoid occurrence of an overhigh temperature; and the discharging modules are spatially separated, which is further favorable for reducing the temperature, releasing the space of the control board and reducing the area of the control board.

Abstract translation: 切线角电路连接到多条扫描线驱动电路，包括：集成在控制板上的充电模块，用于接收直流（DC）驱动电压的输入，并输出一个插入电压以对扫描线驱动进行充电 电路; 以及分别集成在扫描线驱动电路上的多个放电模块，以控制相应的扫描线驱动电路放电。 在本发明中，通过分别在每条扫描线驱动电路上分配放电模块，降低放电模块上的负载放电电荷的负担，以避免发生超高温度; 并且放电模块在空间上分离，这进一步有利于降低温度，释放控制板的空间并减小控制板的面积。

公开(公告)号：US20120292744A1

公开(公告)日：2012-11-22

申请号：US13476748

申请日：2012-05-21

Applicant: Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chia-Ming CHENG ,  Po-Shen LIN

Inventor： Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chia-Ming CHENG ,  Po-Shen LIN

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L21/682 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a substrate, wherein the substrate is diced from a wafer; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a material layer formed on the insulating layer, wherein the material layer has a recognition mark, and the recognition mark shows position information of the substrate in the wafer before the substrate is diced from the wafer.

Abstract translation: 本发明的实施例提供了一种芯片封装，其包括：衬底，其中所述衬底从晶片切割; 形成在所述基板中的器件区域; 导电层，其设置在所述基板上并电连接到所述器件区域; 设置在所述基板和所述导电层之间的绝缘层; 以及形成在所述绝缘层上的材料层，其中所述材料层具有识别标记，并且所述识别标记在从所述晶片切割所述基板之前，示出所述晶片中的所述基板的位置信息。

公开(公告)号：US20110156074A1

公开(公告)日：2011-06-30

申请号：US12981600

申请日：2010-12-30

Applicant: Tsang-Yu LIU ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

Inventor： Tsang-Yu LIU ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

IPC: H01L33/60 ,  H01L33/48

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a chip package, including: a chip having a semiconductor device thereon; a cap layer over the semiconductor device; a spacer layer between the chip and the cap layer, wherein the spacer layer surrounds the semiconductor device and forms a cavity between the chip and the cap layer; and an anti-reflective layer between the cap layer and the chip, wherein the anti-reflective layer has a overlapping region with the spacer layer and extends into the cavity. Furthermore, a method for fabricating a chip package is also provided.

Abstract translation: 本发明提供了一种芯片封装，包括：其上具有半导体器件的芯片; 半导体器件上的覆盖层; 在所述芯片和所述盖层之间的间隔层，其中所述间隔层围绕所述半导体器件并且在所述芯片和所述盖层之间形成空腔; 以及在所述盖层和所述芯片之间的抗反射层，其中所述抗反射层具有与所述间隔层的重叠区域并延伸到所述空腔中。 此外，还提供了一种用于制造芯片封装的方法。