公开(公告)号：US20140170834A1

公开(公告)日：2014-06-19

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics, Inc. ,  STMicroelectronics S.A.

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US20040264250A1

公开(公告)日：2004-12-30

申请号：US10789449

申请日：2004-02-26

Applicant: STMicroelectronics S.A.

Inventor： Sebastien Zink ,  Bruno Leconte ,  Paola Cavaleri

IPC: G11C016/04

CPC classification number: G11C16/3436 ,  G11C16/04 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/50004

Abstract: An electrically erasable and programmable memory includes memory cells and a verify-program device. The memory also comprises an erase verify device arranged for supplying an erase verify signal having a determined value when a datum read in a memory cell during a first verify-program cycle has an erase logic value. Application particularly to performing a blank verify test in serial input/output Flash memories.

Abstract translation: 电可擦除和可编程存储器包括存储器单元和验证程序设备。 存储器还包括擦除验证装置，其被布置为当在第一验证程序周期期间在存储器单元中读取的数据具有擦除逻辑值时，提供具有确定值的擦除验证信号。 特别适用于在串行输入/输出闪存中执行空白验证测试。

公开(公告)号：US20040264228A1

公开(公告)日：2004-12-30

申请号：US10717223

申请日：2003-11-19

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: G11C017/00

CPC classification number: G11C7/067 ,  G11C17/123

Abstract: The invention concerns a ROM circuit (40) comprising columns of storage cells, each column being connected to a bit site (BLi, BLinull1), wherein the columns are arranged in groups of two adjacent columns, each column of a group capable of being selectively activated relative to the other column of the group, thereby enabling the elimination of a connection to the ground of columns and the design of efficient reading amplifiers.

公开(公告)号：US20040262690A1

公开(公告)日：2004-12-30

申请号：US10817147

申请日：2004-04-02

Applicant: STMicroelectronics S.A.

Inventor： Philippe Coronel ,  Yves Morand ,  Thomas Skotnicki ,  Robin Cerutti

IPC: H01L027/148 ,  H01L029/768 ,  H01L029/76 ,  H01L021/336

CPC classification number: H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78645 ,  H01L29/78648

Abstract: A MOS transistor formed in a silicon substrate comprising an active area surrounded with an insulating wall, a first conductive strip covering a central strip of the active area, one or several second conductive strips placed in the active area right above the first strip, and conductive regions placed in two recesses of the insulating wall and placed against the ends of the first and second strips, the silicon surfaces opposite to the conductive strips and regions being covered with an insulator forming a gate oxide.

Abstract translation: 一种形成在硅衬底中的MOS晶体管，包括被绝缘壁包围的有源区域，覆盖有源区域的中心条带的第一导电条，放置在位于第一条带正上方的有源区域中的一个或多个第二导电条，以及导电 放置在绝缘壁的两个凹部中并且抵靠第一和第二条带的端部放置的区域，与导电条带和区域相对的硅表面被形成栅极氧化物的绝缘体覆盖。

公开(公告)号：US20040230723A1

公开(公告)日：2004-11-18

申请号：US10743564

申请日：2003-12-22

Applicant: STMicroelectronics S.A.

Inventor： Nicolas Rougnon-Glasson

IPC: H04L012/56

CPC classification number: G06F5/10 ,  G06F5/06 ,  H04L7/005 ,  H04L7/02

Abstract: Device for transferring data between two asynchronous systems communicating via a FIFO memory. The first system comprises a write pointer register and the second system comprises a read pointer register to the FIFO. Each pointer register is associated with a primary shadow register and a secondary shadow register. The primary shadow register is located in the same sub-assembly as the pointer register with which it is associated, and episodically receives a copy of this pointer register. The secondary shadow register is located in the other sub-assembly, and episodically receives a copy of the primary shadow register. Thus, each system has its own pointer register, its associated primary shadow register, and the secondary shadow register associated with the pointer register of the other system

Abstract translation: 用于在通过FIFO存储器通信的两个异步系统之间传送数据的设备。 第一系统包括写指针寄存器，第二系统包括到FIFO的读指针寄存器。 每个指针寄存器与主影子寄存器和次级影子寄存器相关联。 主影子寄存器位于与其相关联的指针寄存器的相同子组件中，并且偶然地接收该指针寄存器的副本。 次级影子寄存器位于另一个子组件中，并且偶然地接收主影子寄存器的副本。 因此，每个系统都有自己的指针寄存器，其相关联的主影子寄存器和与其他系统的指针寄存器相关联的次级影子寄存器

公开(公告)号：US20040222074A1

公开(公告)日：2004-11-11

申请号：US10841180

申请日：2004-05-07

Applicant: STMicroelectronics S.A.

Inventor： Guillaume Bouche ,  Daniel Saias

IPC: H01H057/00

CPC classification number: H01H59/0009 ,  H01H61/02 ,  H01H2001/0063 ,  H01H2001/0068 ,  H01H2061/006

Abstract: A multiposition microswitch that includes a cavity, a mobile portion made of a deformable material extending above the cavity, at least three conductive tracks extending on the cavity bottom, and a contact pad on the lower surface of the mobile part. The mobile part is capable of deforming, under the action of a stressing mechanism, from an idle position where the contact pad is distant from the conductive tracks to an on position from among several distinct on positions. The contact pad electrically connects, in each distinct on position, at least two of the at least three conductive tracks, at least one of the conductive tracks connected to the contact pad in each distinct on position being different from the conductive tracks connected to the contact pad in the other distinct on positions.

Abstract translation: 一种多位微动开关，其包括空腔，由空腔上方延伸的可变形材料制成的移动部分，在空腔底部延伸的至少三个导电轨道，以及在所述移动部件的下表面上的接触垫。 移动部件能够在应力机构的作用下从接触垫远离导电轨道的空闲位置变形到几个不同的位置之间的打开位置。 接触焊盘在每个不同的位置上电连接至少三个导电轨道中的至少两个，至少一个导电轨道在每个不同的位置上连接到接触焊盘，其不同于连接到触点的导电轨迹 垫在另一个不同的位置。

公开(公告)号：US20040218876A1

公开(公告)日：2004-11-04

申请号：US10739924

申请日：2003-12-18

Applicant: STMicroelectronics S.A.

Inventor： Olivier Franiatte

IPC: G02B006/36

CPC classification number: H04N5/2254

Abstract: An optical system with an optical package capable of being assembled in advance. The optical package comprises a body that contains an integrated-circuit chip having an optical sensor on its front face, a ring and an optical device intended to be placed in front of the said optical sensor. Adhesive is deposited on the internal thread (3) of the ring (2) and/or on the external thread (7) of the optical device (5). The optical device (5) is screwed into the ring (2) as far as an entered position. The ring (2), which is provided with the optical device (5), is affixed to the body (12) of the package (11). In order to bring the optical device (5) to an adjustment position relative to the said optical sensor (14), the said adjustment position being away from its entered position, the optical device is unscrewed relative to the ring. A treatment (19) is then applied to the adhesive (10) so as to fix the optical device (5) in the said ring (2) at the adjustment position reached.

Abstract translation: 具有能够预先组装的光学封装的光学系统。 该光学封装包括一个主体，该主体包含在其正面上具有光学传感器的集成电路芯片，一个环和一个旨在放置在所述光学传感器前面的光学装置。 粘合剂沉积在环（2）的内螺纹（3）和/或光学装置（5）的外螺纹（7）上。 光学装置（5）旋入到环（2）中，直到输入的位置。 设置有光学装置（5）的环（2）固定到包装（11）的主体（12）上。 为了使光学装置（5）相对于所述光学传感器（14）进入调整位置，所述调节位置远离其进入的位置，光学装置相对于环旋开。 然后将处理（19）施加到粘合剂（10），以便在达到的调节位置将光学装置（5）固定在所述环（2）中。

公开(公告)号：US20040174752A1

公开(公告)日：2004-09-09

申请号：US10701115

申请日：2003-11-04

Applicant: STMICROELECTRONICS S.A.

Inventor： Bernard Ramanadin

IPC: G11C007/00

CPC classification number: G11C7/1054 ,  G06F5/00 ,  G06F13/4072 ,  G11C7/1051 ,  G11C7/106

Abstract: An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N output signals. Only one data input of the enable register receives an enable signal. In this way, the propagation time at the input of the buffer register is reduced.

Abstract translation: 输出缓冲寄存器包括接收给定数量N个输入信号的第一输入触发器寄存器，锁存寄存器，选择寄存器和输出N个输出信号的输出多路复用器。 使能寄存器只有一个数据输入端接收使能信号。 以这种方式，缓冲寄存器的输入端的传播时间减少。

公开(公告)号：US20040165662A1

公开(公告)日：2004-08-26

申请号：US10654582

申请日：2003-09-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Andrea Battistella

IPC: H04N007/12

CPC classification number: H04N7/014 ,  H04N5/145 ,  H04N19/56

Abstract: A method of interpolating images intended to be incorporated, into a sequence of moving images, each between a first original image and a second original image of the sequence, comprises an estimation of a motion vector associated with a given pixel block of a current interpolated image. This estimation comprises the preselection of P first motion vectors associated with first other pixel blocks that are adjacent to the given pixel block in the current interpolated image, for which there is already an estimated motion vector. It also comprises the preselection of at most Q second motion vectors associated respectively with second other pixel blocks adjacent to the given pixel block in the preceding interpolated image. Finally, it comprises the selection of the motion vector which minimizes a cost function from the first and second preselected motion vectors.

Abstract translation: 将要被并入的图像内插到序列中的每个在第一原始图像和第二原始图像之间的运动图像序列的方法包括与当前内插图像的给定像素块相关联的运动矢量的估计 。 该估计包括与当前内插图像中与给定像素块相邻的第一其他像素块相关联的P个第一运动矢量的预选择，对于已经估计的运动矢量。 它还包括与前一内插图像中与给定像素块相邻的第二其他像素块相关联的至多Q个第二运动矢量的预选择。 最后，它包括选择使第一和第二预选运动矢量成本函数最小化的运动矢量。

公开(公告)号：US20040150024A1

公开(公告)日：2004-08-05

申请号：US10702066

申请日：2003-11-05

Applicant: STMICROELECTRONICS S.A.

Inventor： Pascale Mazoyer ,  Alexandre Villaret ,  Thomas Skotnicki

IPC: H01L027/108

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7888

Abstract: An integrated memory circuit includes at least one memory cell formed by a single transistor whose gate (GR) has a lower face insulated from a channel region by an insulation layer containing a succession of potential wells, which are substantially arranged at a distance from the gate and from the channel region in a plane substantially parallel to the lower face of the gate. The potential wells are capable of containing an electric charge which is confined in the plane and can be controlled to move in the plane towards a first confinement region next to the source region or towards a second confinement region next to the drain region so as to define two memory states for the cell.

Abstract translation: 集成存储器电路包括由单个晶体管形成的至少一个存储单元，其栅极（GR）具有通过包含一系列势阱的绝缘层与沟道区域绝缘的下表面，绝缘层基本上布置在与栅极相距一定距离处 并且在基本上平行于栅极的下表面的平面中的沟道区域中。 势阱能够容纳限制在平面中的电荷，并且可以控制其在平面内朝向源极区域旁边的第一限制区域或靠近漏极区域的第二限制区域移动，以便限定 两个单元的内存状态。