公开(公告)号：US5438585A

公开(公告)日：1995-08-01

申请号：US250882

申请日：1994-05-31

Applicant: Eric A. Armour ,  Stephen D. Hersee

Inventor： Eric A. Armour ,  Stephen D. Hersee

IPC: H01S5/12 ,  H01S5/20 ,  H01S5/223 ,  H01S5/34 ,  H01S3/18

CPC classification number: B82Y20/00 ,  H01S5/2231 ,  H01S5/34 ,  H01S5/12 ,  H01S5/205 ,  H01S5/2232 ,  H01S5/2237 ,  H01S5/3409

Abstract: A semiconductor laser diode provides high optical power output in a single diffraction-limited farfield lobe using a conventional Fabry-Perot resonant cavity and a planar well graded index separate confinement heterostructure (QW-GRINSCH) active region. An antiguide region is optically coupled to the active region of the laser. In one embodiment, the antiguide region has a lateral variation in the effective index of refraction that forms a diverging medium that causes higher order optical modes to have higher losses in the resonant cavity. The waveguide medium preferably varies in thickness and the thickness approximates a parabolic function in the lateral direction. The antiguide region is enclosed by GaAs layers to minimize oxidation at material interfaces during device fabrication.

Abstract translation: 半导体激光二极管使用传统的法布里 - 珀罗谐振腔和平面阱分级指数分离限制异质结构（QW-GRINSCH）有源区在单个衍射受限的远场波瓣中提供高光功率输出。 光学耦合到激光器的有源区域。 在一个实施例中，防护区域的有效折射率具有横向变化，其形成发散介质，其导致高阶光学模式在谐振腔中具有更高的损耗。 波导介质优选地在厚度上变化，并且厚度在横向上接近抛物线函数。 防护区域由GaAs层包围，以在器件制造期间最小化材料界面处的氧化。

公开(公告)号：US09106056B1

公开(公告)日：2015-08-11

申请号：US14103587

申请日：2013-12-11

Applicant: Stephen D. Hersee

Inventor： Stephen D. Hersee

IPC: H01S5/34 ,  H01S5/343 ,  H01S5/40 ,  B82Y20/00

CPC classification number: H01S5/34333 ,  B82Y20/00 ,  G02B21/0004 ,  G02B21/06 ,  H01L25/167 ,  H01L27/156 ,  H01L33/18 ,  H01L33/24 ,  H01L2224/11 ,  H01S5/34 ,  H01S5/4025 ,  Y10S977/951

Abstract: According to various embodiments, the present teachings include an array of nanowire devices. The array of nanowire devices comprises a readout integrated circuit (ROIC). An LED array is disposed on the ROIC. The LED array comprises a plurality of LED core-shell structures, with each LED core-shell structure comprising a layered shell enveloping a nanowire core, wherein the layered shell comprises a multi-quantum-well (MQW) active region. The LED array further comprises a p-side electrode enveloping the layered core-shell structure and electrically connecting the ROIC, wherein each p-side electrode has an average thickness ranging from about 100 nm to about 500 nm. A dielectric layer is disposed on the plurality of LED core-shell structures, with each nanowire core disposed through the dielectric to connect with an n-side semiconductor that is situated on the dielectric.

Abstract translation: 根据各种实施例，本教导包括纳米线装置阵列。 纳米线器件阵列包括读出集成电路（ROIC）。 LED阵列设在ROIC上。 LED阵列包括多个LED芯 - 壳结构，每个LED芯 - 壳结构包括包围纳米线芯的分层壳，其中分层壳包括多量子阱（MQW）活性区。 LED阵列还包括包围层叠芯壳结构并电连接ROIC的p侧电极，其中每个p侧电极具有约100nm至约500nm的平均厚度。 介电层设置在多个LED芯 - 壳结构上，其中每个纳米线芯通过电介质设置，以与位于电介质上的n侧半导体连接。

公开(公告)号：US08964020B2

公开(公告)日：2015-02-24

申请号：US12103920

申请日：2008-04-16

Applicant: Stephen D. Hersee

Inventor： Stephen D. Hersee

IPC: H04N9/47 ,  H04N5/243 ,  H04N7/18 ,  G02B21/00 ,  B82Y15/00 ,  B82Y20/00 ,  H01L27/15

CPC classification number: G02B21/0004 ,  B82Y15/00 ,  B82Y20/00 ,  G02B21/00 ,  G02B21/002 ,  G02B21/06 ,  G02B21/36 ,  G02B21/361 ,  H01L27/156 ,  H01L33/0025 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/18 ,  H01L33/24 ,  H01L33/32 ,  H01L33/36 ,  H01L2933/0016

Abstract: Exemplary embodiments provide solid-state microscope (SSM) devices and methods for processing and using the SSM devices. The solid-state microscope devices can include a light emitter array having a plurality of light emitters with each light emitter individually addressable. During operation, each light emitter can be biased in one of three operating states including an emit state, a detect state, and an off state. The light emitter can include an LED (light emitting diode) including, but not limited to, a nanowire based LED or a planar LED to provide various desired image resolutions for the SSM devices. In an exemplary embodiment, for near-field microscopy, the resolution of the SSM microscope can be essentially defined by the pitch p, i.e., center-to-center spacing between two adjacent light emitters, of the light emitter array.

Abstract translation: 示例性实施例提供了用于处理和使用SSM装置的固态显微镜（SSM）装置和方法。 固态显微镜装置可以包括具有多个发光体的光发射器阵列，每个发光体可单独寻址。 在操作期间，每个光发射器可以被偏置在包括发射状态，检测状态和关闭状态的三种操作状态之一中。 光发射器可以包括LED（发光二极管），其包括但不限于基于纳米线的LED或平面LED，以为SSM器件提供各种期望的图像分辨率。 在一个示例性实施例中，对于近场显微镜，SSM显微镜的分辨率可以基本上由光发射器阵列的间距p，即两个相邻发光体之间的中心到中心间隔定义。

公开(公告)号：US08188513B2

公开(公告)日：2012-05-29

申请号：US12246044

申请日：2008-10-06

Applicant: Stephen D. Hersee ,  Xin Wang

Inventor： Stephen D. Hersee ,  Xin Wang

IPC: H01L29/66

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7789

Abstract: Nanowire and larger, post-based HEMTs, arrays of such HEMTs, and methods for their manufacture are provided. In one embodiment, a HEMT can include a III-N based core-shell structure including a core member (e.g., GaN), a shell member (e.g., AlGaN) surrounding a length of the core member and a two-dimensional electron gas (2-DEG) at the interface therebetween. The core member including a nanowire and/or a post can be disposed over a doped buffer layer and a gate material can be disposed around a portion of the shell member. Exemplary methods for making the nanowire HEMTs and arrays of nanowire HEMTs can include epitaxially forming nanowire(s) and epitaxially forming a shell member from each formed nanowire. Exemplary methods for making the post HEMTs and arrays of post HEMTs can include etching a III-N layer to form III-N post(s) followed by formation of the shell member(s).

Abstract translation: 提供了纳米线和更大的后置HEMT，这样的HEMT的阵列及其制造方法。 在一个实施例中，HEMT可以包括基于III-N的核 - 壳结构，其包括芯构件（例如，GaN），围绕芯构件的长度的壳构件（例如，AlGaN）和二维电子气 2-DEG）。 包括纳米线和/或柱的芯构件可以设置在掺杂缓冲层上方，并且栅极材料可以围绕壳构件的一部分设置。 用于制造纳米线HEMT和纳米线HEMT阵列的示例性方法可以包括外延形成纳米线并从每个形成的纳米线外延地形成壳部件。 用于制造后HEMT和后HEMT阵列的示例性方法可以包括蚀刻III-N层以形成III-N柱，随后形成壳构件。

公开(公告)号：US20100276664A1

公开(公告)日：2010-11-04

申请号：US12237469

申请日：2008-09-25

Applicant: Stephen D. Hersee

Inventor： Stephen D. Hersee

IPC: H01L29/15 ,  H01L21/20 ,  H01L29/20 ,  H01L29/12

CPC classification number: C30B29/60 ,  B82Y20/00 ,  B82Y30/00 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L31/0304 ,  H01L31/035236 ,  H01L31/184 ,  H01L33/18 ,  H01L33/24 ,  H01S5/10 ,  H01S5/18 ,  H01S5/34 ,  H01S5/3428 ,  Y02E10/544 ,  Y10S977/816

Abstract: Various embodiments provide thin-walled structures and methodologies for their formation. In one embodiment, the thin-walled structure can be formed by disposing a semiconductor material in a patterned aperture using a selective growth mask that includes a plurality of patterned apertures, followed by a continuous growth of the semiconductor material using a pulsed growth mode. The patterned aperture can include at least one lateral dimension that is small enough to allow a threading defect termination at sidewall(s) of the formed thin-walled structure. In addition, high-quality III-N substrate structures and core-shell MQW active structures can be formed from the thin-walled structures for use in devices like light emitting diodes (LEDs), lasers, or high electron mobility transistors (HEMTs).

Abstract translation: 各种实施例提供了用于其形成的薄壁结构和方法。 在一个实施例中，薄壁结构可以通过使用包括多个图案化孔的选择性生长掩模将半导体材料设置在图案化孔中形成，随后使用脉冲生长模式连续生长半导体材料。 图案化的孔可以包括至少一个足够小的横向尺寸，以允许在形成的薄壁结构的侧壁处的穿线缺陷终止。 此外，可以从用于诸如发光二极管（LED），激光器或高电子迁移率晶体管（HEMT）的器件中的薄壁结构形成高质量的III-N衬底结构和核 - 壳MQW有源结构。

公开(公告)号：US06841456B2

公开(公告)日：2005-01-11

申请号：US10418018

申请日：2003-04-17

Applicant: Stephen D. Hersee ,  Ronghua Wang ,  David Zubia ,  Terrance L. Aselage ,  David Emin

Inventor： Stephen D. Hersee ,  Ronghua Wang ,  David Zubia ,  Terrance L. Aselage ,  David Emin

IPC: G21H1/02 ,  G21H1/06 ,  H01L21/20 ,  C30B1/00 ,  H01L21/36

CPC classification number: G21H1/02 ,  G21H1/06 ,  G21Y2002/201 ,  G21Y2002/304 ,  G21Y2004/10 ,  G21Y2004/30 ,  Y10S438/931

Abstract: A method for fabricating thin films of an icosahedral boride on a silicon carbide (SiC) substrate is provided. Preferably the icosahedral boride layer is comprised of either boron phosphide (B12P2) or boron arsenide (B12As2). The provided method achieves improved film crystallinity and lowered impurity concentrations. In one aspect, an epitaxially grown layer of B12P2 with a base layer or substrate of SiC is provided. In another aspect, an epitaxially grown layer of B12As2 with a base layer or substrate of SiC is provided. In yet another aspect, thin films of B12P2 or B12As2 are formed on SiC using CVD or other vapor deposition means. If CVD techniques are employed, preferably the deposition temperature is above 1050° C., more preferably in the range of 1100° C. to 1400° C., and still more preferably approximately 1150° C.

Abstract translation: 提供了一种在碳化硅（SiC）衬底上制造二十面体硼化物薄膜的方法。 优选地，二十面体硼化物层由磷化硼（B12P2）或砷化硼（B12As2）组成。 所提供的方法实现了改善的膜结晶度和降低的杂质浓度。 在一个方面，提供了具有SiC的基底层或衬底的B12P2的外延生长层。 在另一方面，提供了具有SiC的基底层或衬底的B12As2的外延生长层。 在另一方面，使用CVD或其它气相沉积方法在SiC上形成B12P2或B12As2的薄膜。 如果使用CVD技术，则优选沉积温度高于1050℃，更优选在1100℃至1400℃的范围内，还更优选约1150℃。

公开(公告)号：US06596377B1

公开(公告)日：2003-07-22

申请号：US09535732

申请日：2000-03-27

Applicant: Stephen D. Hersee ,  David Zubia ,  Steven R. J. Brueck ,  Saleem H. Zaidi

Inventor： Stephen D. Hersee ,  David Zubia ,  Steven R. J. Brueck ,  Saleem H. Zaidi

IPC: C30B2502

CPC classification number: C30B25/02 ,  C30B29/06 ,  C30B29/403 ,  C30B29/406 ,  C30B29/605 ,  Y10T428/24802 ,  Y10T428/249967

Abstract: A new and useful technique for growing an epilayer onto a substrate is provided. An epilayer is grown on a substrate by (a) providing a patterned substrate comprising a plurality of isolated nanoscale nucleation sites, and (b) growing an epilayer selectively on the nanoscale nucleation sites, in a manner which localizes strain at the substrate-epilayer interface, and enables strain to reduce as the thickness of the epilayer increases.

Abstract translation: 提供了一种用于在衬底上生长外延层的新技术。 通过（a）提供包含多个分离的纳米级成核位点的图案化衬底，并且（b）以在衬底 - 外延层界面上定位应变的方式在纳米尺度成核位置选择性地生长外延层，在衬底上生长外延层 ，并且随着外延层的厚度增加，应变可以减小。

公开(公告)号：US20130240832A1

公开(公告)日：2013-09-19

申请号：US13875264

申请日：2013-05-01

Applicant: Stephen D. Hersee

Inventor： Stephen D. Hersee

IPC: H01L27/15 ,  H01L33/06

CPC classification number: H01L27/15 ,  H01L25/167 ,  H01L29/2003 ,  H01L29/7787 ,  H01L33/0041 ,  H01L33/06 ,  H01L2224/32225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments provide materials and methods for integrating exemplary heterostructure field-effect transistor (HFET) driver circuit or thyristor driver circuit with LED structures to reduce or eliminate resistance and/or inductance associated with their conventional connections.

Abstract translation: 各种实施例提供用于将示例性异质结构场效应晶体管（HFET）驱动器电路或晶闸管驱动器电路与LED结构集成以减少或消除与其常规连接相关联的电阻和/或电感的材料和方法。

公开(公告)号：US08410496B2

公开(公告)日：2013-04-02

申请号：US13231559

申请日：2011-09-13

Applicant: Stephen D. Hersee ,  Xin Wang ,  Xinyu Sun

Inventor： Stephen D. Hersee ,  Xin Wang ,  Xinyu Sun

IPC: H01L29/205 ,  H01L33/00

CPC classification number: H01L29/413 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y30/00 ,  C30B29/60 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/02609 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02642 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/2003 ,  H01L29/775 ,  H01L31/0304 ,  H01L31/035236 ,  H01L31/184 ,  H01L33/18 ,  H01L33/24 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01S5/1042 ,  H01S5/1835 ,  H01S5/18369 ,  H01S5/3428 ,  Y02E10/544 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/816 ,  Y10T428/24612 ,  H01L2924/00

Abstract: Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed group III-N nanowires and/or nanowire arrays providing a uniform length of about 10 nm to about 1000 microns with constant cross-sectional features including an exemplary diameter of about 10-1000 nm. In addition, high-quality GaN substrate structures can be formed by coalescing the plurality of GaN nanowires and/or nanowire arrays to facilitate the fabrication of visible LEDs and lasers. Furthermore, core-shell nanowire/MQW active structures can be formed by a core-shell growth on the nonpolar sidewalls of each nanowire.

公开(公告)号：US08338818B1

公开(公告)日：2012-12-25

申请号：US12635151

申请日：2009-12-10

Applicant: Stephen D. Hersee

Inventor： Stephen D. Hersee

IPC: H01L29/06

CPC classification number: H01L29/0676 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/02609 ,  H01L21/02639 ,  H01L29/2003 ,  H01L29/7787

Abstract: Various embodiments provide non-planar nanowires, nanowire arrays, and nanowire networks as well as methods of their formation and applications. The non-planar nanowires and their arrays can be formed in a controlled manner on surfaces having a non-planar orientation. In embodiments, two or more adjacent nanowires from different surfaces can grow to merge together forming one or more nanowire branches and thus forming a nanowire network. In embodiments, the non-planar nanowires and nanowire networks can be used for cantilever oscillation, switching and transistor actions.

Abstract translation: 各种实施例提供非平面纳米线，纳米线阵列和纳米线网络以及它们的形成和应用的方法。 非平面纳米线及其阵列可以以受控的方式形成在具有非平面取向的表面上。 在实施例中，来自不同表面的两个或更多个相邻的纳米线可以生长以合并在一起形成一个或多个纳米线分支，从而形成纳米线网络。 在实施例中，非平面纳米线和纳米线网络可用于悬臂振荡，开关和晶体管动作。