公开(公告)号：US10437736B2

公开(公告)日：2019-10-08

申请号：US15852442

申请日：2017-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Eric Van Tassell ,  Mark Oskin ,  Guilherme Cox ,  Gabriel Loh

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/1027 ,  G06F9/38 ,  G06F13/40 ,  G06F9/48 ,  G06F13/42

Abstract: A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.

公开(公告)号：US10394726B2

公开(公告)日：2019-08-27

申请号：US15229708

申请日：2016-08-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel Loh

IPC: G06F13/28 ,  G06F13/16

Abstract: A memory network includes a plurality of memory nodes each identifiable by an ordinal number m, and a set of links divided into N subsets of links, where each subset of links is identifiable by an ordinal number n. For each subset of the plurality of N subsets of links, each link in the subset connects two memory nodes that have ordinal numbers m differing by b(n-1), where b is a positive number. Each of the memory nodes is communicatively coupled to a processor via at least two non-overlapping pathways through the plurality of links.

公开(公告)号：US20190196978A1

公开(公告)日：2019-06-27

申请号：US15852442

申请日：2017-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Eric Van Tassell ,  Mark Oskin ,  Guilherme Cox ,  Gabriel Loh

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F9/38 ,  G06F13/40 ,  G06F13/42 ,  G06F9/48

CPC classification number: G06F12/1009 ,  G06F9/3887 ,  G06F9/4843 ,  G06F12/1027 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2213/0026

Abstract: A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.

公开(公告)号：US20170357583A1

公开(公告)日：2017-12-14

申请号：US15181415

申请日：2016-06-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Boyer ,  Gabriel Loh ,  Nuwan Jayasena

IPC: G06F12/0804 ,  G06F12/0842 ,  G06F12/0806

CPC classification number: G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F2212/1016 ,  G06F2212/502 ,  G06F2212/70

Abstract: Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.

公开(公告)号：US20160041914A1

公开(公告)日：2016-02-11

申请号：US14451929

申请日：2014-08-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Gabriel Loh

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0888 ,  G06F2212/602 ,  G06F2212/6046 ,  Y02D10/13

Abstract: Embodiments include methods, systems, and computer readable medium directed to cache bypassing based on prefetch streams. A first cache receives a memory access request. The request references data in the memory. The data comprises non-reuse data. After a determination of a miss in the first cache, the first cache forwards the memory access request to a cache control logic. The detection of the non-reuse data instructs the cache control logic to allocate a block only in a second cache and bypass allocating a block in the first cache. The first cache is closer to the memory than the second cache.

Abstract translation: 实施例包括基于预取流的针对缓存旁路的方法，系统和计算机可读介质。 第一缓存接收存储器访问请求。 请求引用内存中的数据。 数据包括非重用数据。 在确定第一缓存中的未命中之后，第一缓存将存储器访问请求转发到高速缓存控制逻辑。 非重用数据的检测指示高速缓存控制逻辑仅在第二高速缓存中分配块，并且绕过在第一高速缓存中分配块。 第一个缓存比第二个缓存更接近内存。

公开(公告)号：US10133678B2

公开(公告)日：2018-11-20

申请号：US14012475

申请日：2013-08-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Syed Ali Jafri ,  Srilatha Manne ,  Gabriel Loh

IPC: G06F12/00 ,  G06F12/126

Abstract: In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.

公开(公告)号：US20170161194A1

公开(公告)日：2017-06-08

申请号：US14957526

申请日：2015-12-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel Loh

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/1021 ,  G06F2212/507 ,  G06F2212/602 ,  G06F2212/6024 ,  G06F2212/684

Abstract: A method of prefetching data includes issuing to a translation lookaside buffer (TLB) an address translation request for a virtual memory address, detecting a TLB miss generated in response to the address translation request, and in response to the TLB miss, selecting the data for prefetching from memory based on the memory address causing the TLB miss and prefetching the selected data to a cache.

公开(公告)号：US09377954B2

公开(公告)日：2016-06-28

申请号：US14273751

申请日：2014-05-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel Loh ,  Mitesh Meswani ,  Michael Ignatowski ,  Mark Nutter

IPC: H01L29/00 ,  G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0605 ,  G06F3/0631 ,  G06F3/0685 ,  G06F12/023 ,  G06F2212/205 ,  Y02D10/13

Abstract: A system for memory allocation in a multiclass memory system includes a processor coupleable to a plurality of memories sharing a unified memory address space, and a library store to store a library of software functions. The processor identifies a type of a data structure in response to a memory allocation function call to the library for allocating memory to the data structure. Using the library, the processor allocates portions of the data structure among multiple memories of the multiclass memory system based on the type of the data structure.

Abstract translation: 用于多类存储器系统中的存储器分配的系统包括可耦合到共享统一存储器地址空间的多个存储器的处理器和用于存储软件功能库的库存储。 处理器响应于对库的存储器分配功能调用来分配存储器到数据结构来识别数据结构的类型。 使用库，处理器基于数据结构的类型在多类存储器系统的多个存储器之间分配数据结构的一部分。

公开(公告)号：US08880809B2

公开(公告)日：2014-11-04

申请号：US13663335

申请日：2012-10-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel Loh ,  James O'Connor

IPC: G06F13/00

CPC classification number: G06F11/3433 ,  G06F11/349 ,  G06F13/1663 ,  G06F2201/86 ,  G06F2201/88

Abstract: Embodiments are described for a method for controlling access to memory in a processor-based system comprising monitoring a number of interference events, such as bank contentions, bus contentions, row-buffer conflicts, and increased write-to-read turnaround time caused by a first core in the processor-based system that causes a delay in access to the memory by a second core in the processor-based system; deriving a control signal based on the number of interference events; and transmitting the control signal to one or more resources of the processor-based system to reduce the number of interference events from an original number of interference events.

Abstract translation: 描述了用于在基于处理器的系统中控制对存储器的访问的方法的实施例，包括监视多个干扰事件，例如银行争用，总线争用，行缓冲器冲突以及由 基于处理器的系统中的第一核心，其导致在基于处理器的系统中由第二核心访问存储器的延迟; 基于干扰事件的数量导出控制信号; 以及将所述控制信号发送到所述基于处理器的系统的一个或多个资源，以从原始数量的干扰事件减少干扰事件的数量。

公开(公告)号：US20140173225A1

公开(公告)日：2014-06-19

申请号：US13719710

申请日：2012-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Niladrish Chatterjee ,  James O'Connor ,  Gabriel Loh ,  Nuwan Jayasena

IPC: G06F12/00

CPC classification number: G06F9/3887 ,  G06F9/3824

Abstract: Apparatus, computer readable medium, and method of servicing memory requests are presented. A first plurality of memory requests are associated together, wherein each of the first plurality of memory requests is generated by a corresponding one of a first plurality of processors, and wherein each of the first plurality of processors is executing a first same instruction. A second plurality of memory requests are associated together, wherein each of the second plurality of memory requests is generated by a corresponding one of a second plurality of processors, and wherein each of the second plurality of processors is executing a second same instruction. A determination is made to service the first plurality of memory requests before the second plurality of memory requests and the first plurality of memory requests is serviced before the second plurality of memory requests.

Abstract translation: 提供了设备，计算机可读介质和服务存储器请求的方法。 第一多个存储器请求被关联在一起，其中第一多个存储器请求中的每一个由第一多个处理器中的对应的一个处理器生成，并且其中第一多个处理器中的每一个正在执行第一个相同的指令。 第二多个存储器请求被关联在一起，其中第二多个存储器请求中的每一个由第二多个处理器中的对应的一个处理器生成，并且其中第二多个处理器中的每一个正在执行第二个相同的指令。 确定在第二多个存储器请求之前服务第一多个存储器请求，并且在第二多个存储器请求之前服务第一多个存储器请求。