公开(公告)号：US20240155758A1

公开(公告)日：2024-05-09

申请号：US17981338

申请日：2022-11-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Yuan-Chun TAI ,  Yu Hsin CHANG CHIEN ,  Chiu-Wen LEE ,  Chang Chi LEE

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0271 ,  H05K1/11 ,  H05K1/182 ,  H05K2201/068 ,  H05K2201/1003

Abstract: An electronic device is provided. The electronic device includes a first dielectric layer, an electronic element, an encapsulant, and a second dielectric layer. The first dielectric layer has a first coefficient of thermal expansion (CTE). The electronic element is disposed over the first dielectric layer. The encapsulant encapsulates the electronic element and has a second CTE. The second dielectric layer is disposed over the encapsulant and having a third CTE. The second CTE ranges between the first CTE and the third CTE.

公开(公告)号：US20160358875A1

公开(公告)日：2016-12-08

申请号：US15239745

申请日：2016-08-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Hsiang HSIAO ,  Chiu-Wen LEE ,  Ping-Feng YANG ,  Kwang-Lung LIN

IPC: H01L23/00 ,  H01L25/00 ,  C22C9/02 ,  B23K35/26 ,  B23K1/00 ,  C22C13/00 ,  H01L25/065 ,  B23K35/30

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/302 ,  B23K2101/40 ,  C22C9/02 ,  C22C13/00 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/1182 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.

Abstract translation: 半导体器件包括第一电路层，邻近第一电路层设置的铜柱，第二电路层和焊料层。 第二电路层包括电接触和设置在电接触上的表面光洁度层，其中表面光洁度层的材料是镍，金和钯中的至少两种的组合。 焊料层设置在铜柱和表面光洁剂层之间。 焊料层包括第一金属间化合物（IMC）和第二IMC，其中第一IMC包括铜，镍和锡中的两种或更多种的组合，第二IMC包括金和锡的组合，钯的组合 和锡，或两者。

公开(公告)号：US20240345315A1

公开(公告)日：2024-10-17

申请号：US18135075

申请日：2023-04-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Yen TING ,  Hung-Chun KUO ,  Jung Jui KANG ,  Chiu-Wen LEE ,  Shih-Yuan SUN

IPC: G02B6/122 ,  G02B6/12

CPC classification number: G02B6/1225 ,  G02B6/12002 ,  G02B2006/12147

Abstract: An optoelectronic package is provided. The optoelectronic package includes a photonic structure, an alignment component and a light transmission element. The photonic structure includes an optical I/O. The alignment component includes a through hole extending through the alignment component and aligned with the optical I/O of the photonic structure. The light transmission element entirely fills the through hole of the alignment component.

公开(公告)号：US20240329300A1

公开(公告)日：2024-10-03

申请号：US18127624

申请日：2023-03-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-I WU ,  Chun-Yen TING ,  Hung-Chun KUO ,  Jung Jui KANG ,  Chiu-Wen LEE ,  Shih-Yuan SUN

IPC: G02B6/12 ,  H04B10/50

CPC classification number: G02B6/12004 ,  H04B10/501

Abstract: A package device and an electronic device are provided. The package device includes a carrier and a die. The die is disposed over the carrier and has a first surface facing the carrier and a second surface opposite to the first surface. The first surface of the die is configured to electrically connect to the carrier and the second surface of the die is configured to optically connect to the carrier.

公开(公告)号：US20230207524A1

公开(公告)日：2023-06-29

申请号：US18115743

申请日：2023-02-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chi LEE ,  Jung Jui KANG ,  Chiu-Wen LEE ,  Li Chieh CHEN

IPC: H01L25/065 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5387 ,  H01L23/5386 ,  H01L23/5385

Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.

公开(公告)号：US20210265273A1

公开(公告)日：2021-08-26

申请号：US16798152

申请日：2020-02-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Chiu-Wen LEE ,  Ian HU ,  Chang Chi LEE

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48

Abstract: A semiconductor device package includes a plurality of semiconductor chips and an interposer structure. The interposer structure has a plurality of tiers for accommodating the plurality of semiconductor chips. The interposer structure includes at least one conductive via connecting to a pad of the plurality of semiconductor chips.

公开(公告)号：US20180114762A1

公开(公告)日：2018-04-26

申请号：US15299236

申请日：2016-10-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Ta CHIU ,  Chiu-Wen LEE ,  Dao-Long CHEN ,  Po-Hsien SUNG ,  Ping-Feng YANG ,  Kwang-Lung LIN

IPC: H01L23/60 ,  H01L23/31 ,  H01L23/06 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/60 ,  H01L21/56 ,  H01L21/565 ,  H01L23/06 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/49 ,  H01L2224/48091

Abstract: A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.