公开(公告)号：US20240264368A1

公开(公告)日：2024-08-08

申请号：US18105702

申请日：2023-02-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hung-Chun KUO ,  Jung Jui KANG ,  Chiu-Wen LEE ,  Shih-Yuan SUN ,  Chang Chi LEE ,  Chun-Yen TING

IPC: G02B6/12

CPC classification number: G02B6/12004 ,  G02B2006/12109 ,  H04B10/25891

Abstract: An optoelectronic device is provided. The optoelectronic device includes a plurality of first waveguides and a plurality of second waveguides. The plurality of first waveguides are configured to receive a first plurality of optical signals. The plurality of second waveguides are configured to transmit a second plurality of optical signals. The plurality of first waveguides extend substantially along a first direction and the plurality of second waveguides extend substantially along a second direction different from and non-parallel with the first direction.

公开(公告)号：US20220392871A1

公开(公告)日：2022-12-08

申请号：US17338600

申请日：2021-06-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chi LEE ,  Jung Jui KANG ,  Chiu-Wen LEE ,  Li Chieh CHEN

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.

公开(公告)号：US20160260677A1

公开(公告)日：2016-09-08

申请号：US14639535

申请日：2015-03-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Hsiang HSIAO ,  Chiu-Wen LEE ,  Ping-Feng YANG ,  Kwang-Lung LIN

IPC: H01L23/00

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/302 ,  B23K2101/40 ,  C22C9/02 ,  C22C13/00 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/1182 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor die, a semiconductor element and a solder layer. The semiconductor die includes a copper pillar. The semiconductor element includes a surface finish layer, wherein the material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of at least two of copper, nickel and tin. The second IMC is a combination of gold and tin, a combination of palladium and tin, or both.

Abstract translation: 本公开涉及一种半导体器件及其制造方法。 半导体器件包括半导体管芯，半导体元件和焊料层。 半导体管芯包括铜柱。 半导体元件包括表面光洁度层，其中表面光洁度层的材料是镍，金和钯中的至少两种的组合。 焊料层设置在铜柱和表面光洁度层之间。 焊料层包括第一金属间化合物（IMC）和第二IMC，其中第一IMC包括铜，镍和锡中的至少两种的组合。 第二个IMC是金和锡的组合，钯和锡的组合，或两者兼而有之。

公开(公告)号：US20250022848A1

公开(公告)日：2025-01-16

申请号：US18904050

申请日：2024-10-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chi LEE ,  Jung Jui KANG ,  Chiu-Wen LEE ,  Li Chieh CHEN

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.

公开(公告)号：US20240332192A1

公开(公告)日：2024-10-03

申请号：US18128988

申请日：2023-03-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-I WU ,  Chun-Yen TING ,  Hung-Chun KUO ,  Jung Jui KANG ,  Chiu-Wen LEE ,  Shih-Yuan SUN

IPC: H01L23/538 ,  G02B6/12 ,  H01L23/00 ,  H01L23/36 ,  H01L25/16

CPC classification number: H01L23/5381 ,  G02B6/12004 ,  H01L23/36 ,  H01L24/16 ,  H01L25/167 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A package structure is provided. The package structure includes a bridge component, a photonic processing unit, and an electrical device. The photonic processing unit is disposed over the bridge component. The electrical device is disposed over the bridge component. The bridge component is configured to optically couple with the photonic processing unit and electrically connect with the electronic component.

公开(公告)号：US20230163077A1

公开(公告)日：2023-05-25

申请号：US17535400

申请日：2021-11-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chi LEE ,  Chiu-Wen LEE ,  Jung Jui KANG

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L25/0655 ,  H01L23/5386

Abstract: An electronic package is provided. The electronic package includes a semiconductor substrate. The semiconductor substrate includes a first active region and a first passive region separated from the first active region. The first active region is configured to regulate a power signal. The first passive region is configured to transmit a data signal.

公开(公告)号：US20210265231A1

公开(公告)日：2021-08-26

申请号：US16799751

申请日：2020-02-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Chiu-Wen LEE ,  Hung-Jung TU ,  Chang Chi LEE ,  Chin-Li KAO

IPC: H01L23/367 ,  H01L23/48 ,  H01L23/00 ,  H01L21/48

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.

公开(公告)号：US20240345341A1

公开(公告)日：2024-10-17

申请号：US18135076

申请日：2023-04-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jung Jui KANG ,  Shih-Yuan SUN ,  Chiu-Wen LEE ,  Chang Chi LEE ,  Chun-Yen TING ,  Hung-Chun KUO

IPC: G02B6/42 ,  G02B6/43

CPC classification number: G02B6/4267 ,  G02B6/4257 ,  G02B6/43

Abstract: A package device is provided. The package device includes a first die and a first through via structure. The first die has a first optical I/O. The first through via structure is over the first die. A first region of the first through via structure is configured to dissipate heat from the first die and a second region of the first through via structure is configured to transmit an optical signal to or from the first optical I/O.

公开(公告)号：US20240329344A1

公开(公告)日：2024-10-03

申请号：US18129769

申请日：2023-03-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jung Jui KANG ,  Chiu-Wen LEE ,  Shih-Yuan SUN ,  Chang Chi LEE ,  Hung-Chun KUO ,  Chun-Yen TING

IPC: G02B6/43 ,  G02B6/42 ,  H01L25/16

CPC classification number: G02B6/43 ,  G02B6/4206 ,  G02B6/4239 ,  H01L25/167

Abstract: Semiconductor packages and methods for manufacturing the semiconductor packages are provided. The semiconductor package includes a first electronic element disposed over a first substrate; a second electronic element disposed over a second substrate spaced apart from the first substrate; and a first interconnection element connected to the first electronic element and the second electronic element. The first electronic element extends beyond an edge of the first substrate. The second electronic element extends beyond an edge of the second substrate and towards the first electronic element. The first interconnection element is configured to optically transmit a signal between the first electronic element and the second electronic element.

公开(公告)号：US20240250030A1

公开(公告)日：2024-07-25

申请号：US18100570

申请日：2023-01-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin CHANG CHIEN ,  Yuan-Chun TAI ,  Chiu-Wen LEE ,  Yu-Hsun CHANG ,  Tai-Yuan HUANG

IPC: H01L23/532 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5329 ,  H01L23/31 ,  H01L23/49816 ,  H01L28/10

Abstract: An electronic device is provided. The electronic device includes an inductor and a dielectric layer. The inductor includes a first magnetic layer, a conductive trace over the first magnetic layer, and a second magnetic layer over the conductive trace. The dielectric layer includes a first portion between the second magnetic layer and an inclined surface of the first magnetic layer. A substantially constant distance between the second magnetic layer and the inclined surface of the first magnetic layer is defined by the dielectric layer.