公开(公告)号：US12062708B2

公开(公告)日：2024-08-13

申请号：US17968068

申请日：2022-10-18

Applicant: Applied Materials, Inc.

Inventor： Michael Stolfi ,  Myungsun Kim ,  Benjamin Colombeau ,  Sanjay Natarajan

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66439 ,  H01L29/0673 ,  H01L29/42392 ,  H01L27/088

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US11923441B2

公开(公告)日：2024-03-05

申请号：US17888894

申请日：2022-08-16

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/455 ,  C23C16/56 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/6681 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/45536 ,  C23C16/56 ,  C30B29/06 ,  C30B29/52 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L29/42392 ,  H01L29/6653

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US20220320318A1

公开(公告)日：2022-10-06

申请号：US17843968

申请日：2022-06-18

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Matthias Bauer ,  Naved Ahmed Siddiqui ,  Phillip Stout

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238

Abstract: Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

公开(公告)号：US11309404B2

公开(公告)日：2022-04-19

申请号：US16502555

申请日：2019-07-03

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/687 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L29/08

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

公开(公告)号：US11189479B2

公开(公告)日：2021-11-30

申请号：US16865514

申请日：2020-05-04

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Johanes F. Swenberg ,  Steven C. H. Hung

IPC: H01L21/469 ,  H01L23/58 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768

Abstract: A method of forming an electronic device is disclosed. The method comprises forming a barrier layer on a silicon layer, and depositing a silicon oxide layer on the barrier layer. The formation of the barrier layer on the silicon layer minimizes parasitic oxidation of the underlying silicon layer and minimizes defects in the silicon layer.

公开(公告)号：US11145761B2

公开(公告)日：2021-10-12

申请号：US16592362

申请日：2019-10-03

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Vanessa Pena ,  Errol Antonio C. Sanchez ,  Benjamin Colombeau ,  Michael Chudzik ,  Bingxi Wood ,  Nam Sung Kim

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US20210119021A1

公开(公告)日：2021-04-22

申请号：US17077153

申请日：2020-10-22

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Matthias Bauer ,  Naved Ahmed Siddiqui ,  Phillip Stout

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238

Abstract: Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

公开(公告)号：US20210119005A1

公开(公告)日：2021-04-22

申请号：US17073505

申请日：2020-10-19

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Hans-Joachim Gossmann

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US20200051818A1

公开(公告)日：2020-02-13

申请号：US16536600

申请日：2019-08-09

Applicant: Applied Materials, Inc.

Inventor： Wolfgang Aderhold ,  Yi-Chiau Huang ,  Wei Liu ,  Benjamin Colombeau ,  Abhilash Mayur

IPC: H01L21/225 ,  H01L21/324

Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

公开(公告)号：US09865735B2

公开(公告)日：2018-01-09

申请号：US15152273

申请日：2016-05-11

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Vanessa Pena ,  Errol Antonio C. Sanchez ,  Benjamin Colombeau ,  Michael Chudzik ,  Bingxi Wood ,  Nam Sung Kim

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78642

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.