公开(公告)号：US20050167782A1

公开(公告)日：2005-08-04

申请号：US11098070

申请日：2005-04-04

Applicant: Hector Sanchez ,  Michael Mendicino ,  Byoung Min ,  Kathleen Ju

Inventor： Hector Sanchez ,  Michael Mendicino ,  Byoung Min ,  Kathleen Ju

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L23/522 ,  H01L27/06 ,  H01L27/12 ,  H01L23/053

CPC classification number: H01L27/0688 ,  H01L21/76838 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.

Abstract translation: 半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连（68）连接的直接下伏的无源器件，例如电容器（75,77,79） ，99）。 通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。 横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。 金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

公开(公告)号：US20050067960A1

公开(公告)日：2005-03-31

申请号：US10946353

申请日：2004-09-22

Applicant: Byoung Min

Inventor： Byoung Min

IPC: H01J11/24 ,  H01J11/36 ,  H01J11/44 ,  H01J17/49

CPC classification number: H01J11/36 ,  H01J11/12 ,  H01J2211/365 ,  H01J2211/444

Abstract: The present invention relates to a plasma display panel, and more particularly, to a cell structure of a plasma display panel. In a plasma display panel in which square cells constitute a delta type barrier rib structure, a red cell and a green cell are alternately formed in a first horizontal cell line of the cells, a blue cell is located at the lower center between the red cell and the green cell in a second horizontal cell line of the cells, the blue cell is alternately formed together with a blank cell, and the first horizontal cell line and the second horizontal cell line are alternately formed in the vertical direction. Accordingly, brightness, efficiency and the contrast ratio are improved and high-speed driving is accomplished.

Abstract translation: 等离子体显示面板技术领域本发明涉及等离子体显示面板，更具体地，涉及等离子体显示面板的单元结构。 在其中方形电池构成三角型阻挡肋结构的等离子体显示面板中，红细胞和绿色电池交替地形成在细胞的第一水平细胞系中，蓝色细胞位于红细胞之间的较低中心 和绿色单元在单元的第二水平单元行中，蓝色单元与空白单元交替地形成，并且第一水平单元线和第二水平单元线在垂直方向上交替地形成。 因此，提高了亮度，效率和对比度，并且实现了高速驱动。

公开(公告)号：US20070161171A1

公开(公告)日：2007-07-12

申请号：US11328668

申请日：2006-01-10

Applicant: James Burnett ,  Leo Mathew ,  Byoung Min

Inventor： James Burnett ,  Leo Mathew ,  Byoung Min

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.

Abstract translation: 用于形成电子器件的工艺可以包括形成用于鳍型结构的第一高度的半导体鳍片，并且去除半导体鳍片的一部分，使得半导体鳍片缩短到第二高度。 根据具体实施例，可以形成第二半导体鳍片，第一和第二半导体鳍片中的每一个具有表示沟道宽度的不同高度。 根据另一具体实施例，可以形成第二和第三半导体鳍片，第一，第二和第三半导体鳍片中的每一个具有代表沟道宽度的不同高度。

公开(公告)号：US20060258053A1

公开(公告)日：2006-11-16

申请号：US11431742

申请日：2006-05-09

Applicant: Doo Lee ,  Chang Ryu ,  Han Cho ,  Byoung Min

Inventor： Doo Lee ,  Chang Ryu ,  Han Cho ,  Byoung Min

IPC: H01L21/00

CPC classification number: H01L24/18 ,  H01L24/82 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/188 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/0959 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Disclosed herein is a method for manufacturing a component-embedded printed circuit board that is economically advantageous and simple. The method is characterized by stacking boards in which a high density of electronic components are mounted to form a core layer in which the electronic components are embedded, and by subsequently building up additional circuit layers.

Abstract translation: 本文公开了一种经济有利且简单的组件嵌入式印刷电路板的制造方法。 该方法的特征在于堆叠板，其中安装高密度的电子部件以形成其中嵌入电子部件的芯层，以及随后构建附加的电路层。

公开(公告)号：US20060145805A1

公开(公告)日：2006-07-06

申请号：US11140680

申请日：2005-05-27

Applicant: Han Kim ,  Byoung Min ,  Young Kim ,  Young Lee ,  Chang Ryu

Inventor： Han Kim ,  Byoung Min ,  Young Kim ,  Young Lee ,  Chang Ryu

IPC: H01F5/00

CPC classification number: H01F5/00 ,  H01F17/0006 ,  H01F17/0033 ,  H01F2017/002 ,  H05K1/165 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/097

Abstract: A printed circuit board (PCB) having a three-dimensional spiral inductor, which includes a plurality of insulating layers and conductor layers. The PCB comprises a plurality of coil conductor patterns made of conductive material and shaped into strips, which is provided on the plurality of conductor layers, respectively, such that the plurality of coil conductor patterns are parallel to each other and positioned on the same plane perpendicular to the conductor layers, and in which each of the plurality of coil conductor patterns is longer than an adjacent inner coil conductor pattern.

Abstract translation: 一种具有三维螺旋电感器的印刷电路板（PCB），其包括多个绝缘层和导体层。 PCB包括由导电材料制成并成形为条的多个线圈导体图案，其分别设置在多个导体层上，使得多个线圈导体图案彼此平行并且位于同一平面上垂直 并且其中多个线圈导体图案中的每一个长于相邻的内部线圈导体图案。

公开(公告)号：US20060061232A1

公开(公告)日：2006-03-23

申请号：US10994459

申请日：2004-11-23

Applicant: Byoung Min ,  Hyoung Jeon ,  Hyun Kim

Inventor： Byoung Min ,  Hyoung Jeon ,  Hyun Kim

IPC: H01L41/09

CPC classification number: H02N2/0075 ,  H02N2/147

Abstract: Disclosed herein is a piezoelectric actuator drive system for forward or backward driving a piezoelectric actuator for zooming and/or focusing in a camera module. The piezoelectric actuator drive system comprises a power supply for supplying an operating voltage, a drive controller for controlling generation of a forward/backward drive signal for a piezoelectric actuator in response to an operation ON select signal and a forward/backward driving select signal, a clock generator for generating a first clock signal in response to the operating voltage from the power supply, and a drive signal generator for generating and supplying the forward or backward drive signal to the piezoelectric actuator in response to the first clock signal from the clock generator and the operating voltage from the power supply under the forward/backward drive signal generation control of the drive controller.

公开(公告)号：US20050269979A1

公开(公告)日：2005-12-08

申请号：US11138465

申请日：2005-05-27

Applicant: Byoung Min ,  Byung Choi ,  Tae Lee

Inventor： Byoung Min ,  Byung Choi ,  Tae Lee

IPC: H02K17/08 ,  H02P1/42 ,  H02P23/00 ,  H02P25/02 ,  H02P25/04 ,  H02P7/08

CPC classification number: H02P25/18 ,  H02P25/04 ,  H02P25/188

Abstract: An outer-rotor variable-speed motor, to which single-phase AC power is applied and on which a rotor is provided outside a stator, comprises first and second main windings provided on a stator of the motor to form a plurality of poles, a frequency detector for detecting the frequency of AC power applied to the motor, and a relay for connecting the first and second main windings in series if the detected frequency is 60 Hz and connecting the first and second main windings in parallel if the detected frequency is 50 Hz. The speed of the motor is kept constant even when power at different frequencies is applied, so that it is possible to reduce the manufacturing cost of the motor and reduce the power consumption, and also to reduce electromagnetic noise from the motor.

Abstract translation: 一个外转子变速电动机，其上施加有单相交流电源并且在定子外部设置转子，包括设置在电动机的定子上以形成多个极的第一和第二主绕组， 频率检测器，用于检测施加到电动机的交流电力的频率;以及继电器，用于如果检测到的频率为60Hz，则将第一和第二主绕组串联连接，并且如果检测到的频率为50，则并联第一和第二主绕组 赫兹。 即使施加不同频率的电力，电动机的速度也保持恒定，从而可以降低电动机的制造成本并降低功率消耗，并且还可以降低电动机的电磁噪声。

公开(公告)号：US20050213653A1

公开(公告)日：2005-09-29

申请号：US10849960

申请日：2004-05-21

Applicant: Byoung Min ,  Hyun Kim ,  Hyoung Jeon

Inventor： Byoung Min ,  Hyun Kim ,  Hyoung Jeon

IPC: G03B3/10 ,  G02B3/14 ,  G02B7/08 ,  G02F1/13 ,  G02F1/133 ,  G02F1/29 ,  G03B13/34 ,  G09G3/36 ,  H01R13/66 ,  H03K7/02 ,  H03K7/08 ,  H04B17/00

CPC classification number: G02F1/13306 ,  G02F1/29

Abstract: A variable square-wave drive device for controlling square waves using feedback- and bias-control methods. The variable square-wave drive device includes an oscillator for generating a clock pulse; a frequency-divider/duty controller for frequency-dividing the clock pulse received from the oscillator to generate a clock signal and a square-wave signal; a drive for amplifying the square-wave signal received from the frequency-divider/duty controller according to a bias voltage, generating first and second square-wave signals having opposite phases, and outputting the first and second square-wave signals as a square-wave drive signal; a feedback controller for comparing a predetermined voltage variable determined by a user with the bias voltage of the drive to generate a comparison result signal; a switching controller for generating a switching signal upon receiving the comparison result signal from the feedback controller; and a bias voltage regulator for charging/discharging the input voltage according to the switching signal received from the switching controller so that it can adjust the bias voltage of the drive.

Abstract translation: 一种使用反馈和偏置控制方法控制方波的可变方波驱动装置。 可变方波驱动装置包括用于产生时钟脉冲的振荡器; 用于对从振荡器接收的时钟脉冲进行分频以产生时钟信号和方波信号的分频器/占空比控制器; 驱动器，用于根据偏置电压放大从分频器/占空比控制器接收的方波信号，产生具有相反相位的第一和第二方波信号，并将第一和第二方波信号输出为方波， 波驱动信号; 用于将由用户确定的预定电压变量与所述驱动器的偏置电压进行比较以产生比较结果信号的反馈控制器; 切换控制器，用于在从反馈控制器接收到比较结果信号时产生切换信号; 以及偏置电压调节器，用于根据从开关控制器接收的开关信号对输入电压进行充电/放电，从而可以调节驱动器的偏置电压。

公开(公告)号：US20050042867A1

公开(公告)日：2005-02-24

申请号：US10946758

申请日：2004-09-22

Applicant: Hector Sanchez ,  Michael Mendicino ,  Byoung Min ,  Kathleen Yu

Inventor： Hector Sanchez ,  Michael Mendicino ,  Byoung Min ,  Kathleen Yu

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L23/522 ,  H01L27/06 ,  H01L27/12 ,  H01L21/20

CPC classification number: H01L27/0688 ,  H01L21/76838 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.

Abstract translation: 半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连（68）连接的直接下伏的无源器件，例如电容器（75,77,79） ，99）。 通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。 横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。 金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

公开(公告)号：US20050020015A1

公开(公告)日：2005-01-27

申请号：US10624398

申请日：2003-07-22

Applicant: Leo Mathew ,  Byoung Min

Inventor： Leo Mathew ,  Byoung Min

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/8236

CPC classification number: H01L29/785 ,  H01L21/823437 ,  H01L27/1203

Abstract: A method for creating a vertical double-gate transistor design includes providing a planar transistor layout (10) having a gate layer (12) overlying an active layer (14). In one embodiment, a first intermediate layer (18) is defined based on an overlapping region of the gate and active layers, and, using the first intermediate layer, a second intermediate layer (22) is defined which defines a spacing between at least two fins of the vertical double-gate transistor design. The second intermediate layer may also define a length and a width of the at least two fins. One embodiment modifies a dimension of the first intermediate layer prior to defining the second intermediate layer. The method further includes defining a resulting layer (24) based on a non-overlapping region of the second intermediate layer and the active layer. The resulting layer may then be used to create a mask and a semiconductor device (30) corresponding to the vertical double-gate transistor design.

Abstract translation: 一种用于产生垂直双栅极晶体管设计的方法包括提供具有覆盖有源层（14）的栅极层（12）的平面晶体管布局（10）。 在一个实施例中，基于栅极和有源层的重叠区域限定第一中间层（18），并且使用第一中间层限定第二中间层（22），其限定了至少两个 翅片垂直双栅极晶体管设计。 第二中间层还可以限定至少两个翅片的长度和宽度。 一个实施例在限定第二中间层之前修改第一中间层的尺寸。 该方法还包括基于第二中间层和有源层的非重叠区域来限定所得层（24）。 所得到的层然后可用于产生对应于垂直双栅极晶体管设计的掩模和半导体器件（30）。