公开(公告)号：US06739930B2

公开(公告)日：2004-05-25

申请号：US09925356

申请日：2001-08-09

Applicant: Huang-Chung Cheng ,  Fu-Gom Tarntair ,  Chia-Pin Lin

Inventor： Huang-Chung Cheng ,  Fu-Gom Tarntair ,  Chia-Pin Lin

IPC: H01J900

CPC classification number: H01J9/025

Abstract: A process of forming a field emission electrode for manufacturing a field emission array is provided. The process includes steps of (a) providing a substrate having a metal layer thereon, (b) forming a plurality of mask units on the metal layer and partially removing the metal layer uncovered by the mask units, (c) oxidizing a surface of the remained metal layer by an anodic oxidization method for forming a metal oxide layer thereon such that an upper portion of the unoxidized remained metal layer is in the shape of plural conoids, and (d) removing the remained mask units and the metal oxide layer. Alternatively, the process includes steps of (a) providing a substrate having a first metal layer thereon, (b) forming a plurality of mask units on the first metal layer and partially removing the first metal layer uncovered by the mask units, (c) oxidizing a surface of the remained first metal layer by an anodic oxidization method for forming a metal oxide layer thereon such that an upper portion of the unoxidized remained first metal layer is in the shape of plural cylinders, (d) forming a second metal layer on the metal oxide layer, and (e) removing the remained mask units.

Abstract translation: 提供了一种形成用于制造场致发射阵列的场致发射电极的工艺。 该方法包括以下步骤：（a）提供其上具有金属层的基底，（b）在金属层上形成多个掩模单元，并部分去除未被掩模单元覆盖的金属层，（c） 通过用于在其上形成金属氧化物层的阳极氧化方法保留金属层，使得未氧化的残留金属层的上部为多个扁桃状，（d）除去残留的掩模单元和金属氧化物层。 或者，该方法包括以下步骤：（a）提供其上具有第一金属层的基底，（b）在第一金属层上形成多个掩模单元，并部分去除未被掩模单元覆盖的第一金属层，（c） 通过用于在其上形成金属氧化物层的阳极氧化方法氧化残留的第一金属层的表面，使得未氧化的残留的第一金属层的上部为多个圆柱体，（d）在第二金属层上形成第二金属层 金属氧化物层，和（e）去除残留的掩模单元。

公开(公告)号：US09312179B2

公开(公告)日：2016-04-12

申请号：US12725554

申请日：2010-03-17

Applicant: Chia-Pin Lin ,  Chien-Tai Chan ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

Inventor： Chia-Pin Lin ,  Chien-Tai Chan ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的finFET的第一和第二鳍片，其间具有浅沟槽隔离（STI）区域，以及STI区域的顶表面与第一鳍片和第二鳍片的顶表面之间的距离。 第一和第二鳍片延伸部分设置在STI区域顶表面上方的第一和第二鳍片的顶表面和侧表面上。 从STI区域去除材料，以增加STI区域的顶表面与第一和第二鳍片的顶表面之间的距离。 保形应力源电介质材料沉积在鳍片和STI区域上。 共形介电应力材料被回流，以流入STI区域的顶表面之上的第一和第二鳍片之间的空间，以向finFET的沟道施加应力。

公开(公告)号：US08921946B2

公开(公告)日：2014-12-30

申请号：US13294251

申请日：2011-11-11

Applicant: King-Yuen Wong ,  Chia-Pin Lin ,  Chia-Yu Lu ,  Yi-Cheng Tsai ,  Da-Wen Lin ,  Kuo-Feng Yu

Inventor： King-Yuen Wong ,  Chia-Pin Lin ,  Chia-Yu Lu ,  Yi-Cheng Tsai ,  Da-Wen Lin ,  Kuo-Feng Yu

IPC: H01L29/772 ,  H01L21/265 ,  H01L27/06 ,  H01L29/8605 ,  H01L29/66

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823437 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/8605

Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.

Abstract translation: 半导体器件包括包括隔离区域的衬底和设置在隔离区域上的电阻器，其中电阻器包括具有反向盒状掺杂物分布的植入物，其使得电阻变化与随后的平坦化变化最小化。 触点设置在电阻上。 还提供了一种制造这种半导体器件的方法。

公开(公告)号：US08796095B2

公开(公告)日：2014-08-05

申请号：US13241014

申请日：2011-09-22

Applicant: Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

Inventor： Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/66803

Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

Abstract translation: 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 植入操作可以在两个氮化物膜沉积操作之间进行。 第一氮化物膜可以是SiNx或SiCNx，第二氮化物膜是SiCNx。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。

公开(公告)号：US08431453B2

公开(公告)日：2013-04-30

申请号：US13077358

申请日：2011-03-31

Applicant: Yu-Lien Huang ,  Chia-Pin Lin ,  Sheng-Hsiung Wang ,  Fan-Yi Hsu ,  Chun-Liang Tai

Inventor： Yu-Lien Huang ,  Chia-Pin Lin ,  Sheng-Hsiung Wang ,  Fan-Yi Hsu ,  Chun-Liang Tai

IPC: H01L21/338

CPC classification number: H01L27/088 ,  H01L29/513 ,  H01L29/66545

Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD0, surrounding the gate structures with a dopant to reduce its etch rates during the processes of removing dummy gate electrode layer and/or gate dielectric layer for replacement gate technologies. The ILD0 film may be doped with a plasma doping process (PLAD) or an ion beam process. Post doping anneal is optional.

Abstract translation: 本文公开的方法和结构的实施例提供了利用掺杂剂围绕栅极结构进行掺杂层间电介质膜ILD0的机制，以在去除伪栅极电极层和/或栅极电介质层的过程中降低其蚀刻速率 替换门技术。 可以用等离子体掺杂工艺（PLAD）或离子束工艺来掺杂ILD0膜。 后掺杂退火是可选的。

公开(公告)号：US08278173B2

公开(公告)日：2012-10-02

申请号：US12827512

申请日：2010-06-30

Applicant: Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

Inventor： Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

IPC: H01L21/8234

CPC classification number: H01L27/092 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: A method includes: forming first and second projections; forming a first structure engaging the first projection, and including: a non-metallic conductive layer, and a first opening over the conductive layer; forming a second structure engaging the second projection, and including: a second opening; and conformally depositing a pure metal in the first and second openings. A different aspect involves an apparatus including: a first device that includes a first projection and a first gate structure, the first projection extending from a substrate, and the first gate structure engaging the first projection, and including an opening, and a conformal, pure metal disposed in the opening; and a second device that includes a second projection and a second gate structure, the second projection extending from the substrate, and the second gate structure engaging the second projection, and including a silicide including a metal that is the same metal disposed in the opening.

Abstract translation: 一种方法包括：形成第一和第二突起; 形成与所述第一突起接合的第一结构，并且包括：非金属导电层和所述导电层上的第一开口; 形成与第二突起接合的第二结构，并且包括：第二开口; 并且在第一和第二开口中共形沉积纯金属。 不同的方面涉及一种装置，包括：第一装置，其包括第一突起和第一栅极结构，第一突起从基板延伸，第一栅极结构与第一突起接合，并且包括开口和保形的纯的 设置在开口中的金属; 以及第二装置，其包括第二突起和第二栅极结构，所述第二突起从所述基板延伸，所述第二栅极结构接合所述第二突起，并且包括包含设置在所述开口中的相同金属的金属的硅化物。

公开(公告)号：US20120001266A1

公开(公告)日：2012-01-05

申请号：US12827512

申请日：2010-06-30

Applicant: Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang- Yuan Hsu

Inventor： Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang- Yuan Hsu

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: A method includes: forming first and second projections; forming a first structure engaging the first projection, and including: a non-metallic conductive layer, and a first opening over the conductive layer; forming a second structure engaging the second projection, and including: a second opening; and conformally depositing a pure metal in the first and second openings. A different aspect involves an apparatus including: a first device that includes a first projection and a first gate structure, the first projection extending from a substrate, and the first gate structure engaging the first projection, and including an opening, and a conformal, pure metal disposed in the opening; and a second device that includes a second projection and a second gate structure, the second projection extending from the substrate, and the second gate structure engaging the second projection, and including a silicide including a metal that is the same metal disposed in the opening.

Abstract translation: 一种方法包括：形成第一和第二突起; 形成与所述第一突起接合的第一结构，并且包括：非金属导电层和所述导电层上的第一开口; 形成与第二突起接合的第二结构，并且包括：第二开口; 并在第一和第二开口中共形沉积纯金属。 不同的方面涉及一种装置，包括：第一装置，其包括第一突起和第一栅极结构，第一突起从基板延伸，第一栅极结构与第一突起接合，并且包括开口和保形的纯的 设置在开口中的金属; 以及第二装置，其包括第二突起和第二栅极结构，所述第二突起从所述基板延伸，所述第二栅极结构接合所述第二突起，并且包括包含设置在所述开口中的相同金属的金属的硅化物。

公开(公告)号：US20050230711A1

公开(公告)日：2005-10-20

申请号：US10710697

申请日：2004-07-29

Applicant: Chin-Chung Chang ,  Chia-Pin Lin ,  Kwang-Shiang Juang ,  Shao- Chien Lee

Inventor： Chin-Chung Chang ,  Chia-Pin Lin ,  Kwang-Shiang Juang ,  Shao- Chien Lee

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/538 ,  H01L27/10 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/5384 ,  H01L2924/0002 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/096 ,  H01L2924/00

Abstract: A connecting circuit structure is provided for a circuit carrier. The circuit connecting structure includes at least two insulating layers, two conductive layers, and one conductive pad, wherein a via hole is formed from each of the insulating layers through corresponding insulating layer. One insulating layer is formed over the other. The conductive pad is disposed between the two insulating layers, and two surfaces of the conductive pad are connected to the two via holes respectively. Two conductive layers are respectively formed in the via hole on a same side of the circuit connecting structure in order to connect to the conductive pad respectively. Since a depth/width ratio of the via hole is reduced according to the circuit connecting structure in the present invention, voids and bubbles are effectively avoided and the reliability of fabricating method thereof is increased.

Abstract translation: 为电路载体提供连接电路结构。 电路连接结构包括至少两个绝缘层，两个导电层和一个导电焊盘，其中通过相应的绝缘层从每个绝缘层形成通孔。 一个绝缘层形成在另一个上。 导电焊盘设置在两个绝缘层之间，导电焊盘的两个表面分别连接到两个通孔。 在电路连接结构的同一侧的通孔中分别形成两个导电层，以分别连接到导电焊盘。 由于根据本发明的电路连接结构减小了通孔的深度/宽度比，因此有效地避免了空隙和气泡，并且其制造方法的可靠性增加。

公开(公告)号：US20050098262A1

公开(公告)日：2005-05-12

申请号：US11015273

申请日：2004-12-16

Applicant: Chia-Pin Lin ,  Chih-Peng Fan ,  Chang-Yun Hung ,  Sheng-Chou Lee

Inventor： Chia-Pin Lin ,  Chih-Peng Fan ,  Chang-Yun Hung ,  Sheng-Chou Lee

IPC: B32B15/04 ,  B32B15/20 ,  H05K3/38 ,  B32B31/26

CPC classification number: B32B15/04 ,  B32B15/20 ,  B32B2037/243 ,  B32B2038/0076 ,  B32B2307/3065 ,  B32B2311/12 ,  B32B2379/08 ,  B32B2457/08 ,  H05K3/386 ,  H05K2201/0355 ,  H05K2203/0143 ,  H05K2203/0759 ,  H05K2203/1366

Abstract: A method of laminating copper foil onto a substrate of a printed circuit board, wherein the substrate has an upper surface and a lower surface. Isolating material is coated onto both surfaces of the substrate to form isolating layers on the substrate. The isolating layers can be formed by roll coating, spray coating or screen printing. The thickness of the isolating layers can be controlled in accordance to the requirements of the circuits. Various types of metal foils can be laminated onto the isolating layers, followed by heating and pressurization processes to secure the metal foil onto the substrate.

Abstract translation: 一种将铜箔层压到印刷电路板的基板上的方法，其中基板具有上表面和下表面。 将隔离材料涂覆在基板的两个表面上以在基板上形成隔离层。 隔离层可以通过辊涂，喷涂或丝网印刷形成。 隔离层的厚度可以根据电路的要求进行控制。 可以将各种类型的金属箔层压到隔离层上，然后进行加热和加压工艺以将金属箔固定到基底上。

公开(公告)号：US08937353B2

公开(公告)日：2015-01-20

申请号：US12714796

申请日：2010-03-01

Applicant: Hung-Kai Chen ,  Hsien-Hsin Lin ,  Chia-Pin Lin ,  Chien-Tai Chan ,  Yuan-Ching Peng

Inventor： Hung-Kai Chen ,  Hsien-Hsin Lin ,  Chia-Pin Lin ,  Chien-Tai Chan ,  Yuan-Ching Peng

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的第一鳍片和第二鳍片，在它们之间具有浅沟槽隔离（STI）区域。 在STI区域的顶表面之上的第一和第二鳍之间限定空间。 第一高度限定在STI区域的顶表面和第一鳍片和第二鳍片的顶表面之间。 可流动的电介质材料沉积到该空间中。 电介质材料具有在STI区域的顶表面上方的顶表面，以便在介电材料的顶表面和第一和第二鳍片的顶表面之间限定第二高度。 第二个高度小于第一个高度。 在沉积步骤之后，第一和第二鳍片延伸部分别外延形成在电介质上方，分别在第一和第二鳍片上。