公开(公告)号：US06750533B2

公开(公告)日：2004-06-15

申请号：US10175217

申请日：2002-06-19

Applicant: Yu-Po Wang ,  Chung-Chi Lin ,  Chien-Ping Huang

Inventor： Yu-Po Wang ,  Chung-Chi Lin ,  Chien-Ping Huang

IPC: H01L23495

CPC classification number: H01L24/85 ,  H01L21/565 ,  H01L23/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/78 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A chip carrier with a dam bar structure is proposed. The chip carrier is defined with at least a chip attach area and a wire bonding area surrounding the chip attach area, allowing a chip to be mounted on the chip attach area and electrically connected to the wire bonding area by bonding wires bonded to the wire bonding area. A molding gate and a dam bar are formed on the substrate outside the chip attach area and wire bonding area. An molding compound is injected through the molding gate for encapsulating the chip and bonding wires. The dam bar is provided with a first gate directed toward the molding gate, a second gate and a third gate opposed to the second gate, wherein the second and third gates are each vertically arranged with respect to the molding gate, allowing the molding compound to divert its flow direction by the dam bar.

Abstract translation: 提出了具有坝条结构的芯片载体。 芯片载体至少具有芯片附着区域和围绕芯片附着区域的引线接合区域，允许将芯片安装在芯片附着区域上，并通过与引线键合的接合线电连接到引线接合区域 区。 在芯片附着区域和引线接合区域的外部的基板上形成模制门和阻挡条。 通过模制注入模塑料以封装芯片和接合线。 坝栏设置有朝向模制门的第一门，与第二门相对的第二门和第三门，其中第二和第三门相对于成型门垂直布置，允许模制化合物 通过坝条转向其流动方向。

公开(公告)号：US08183092B2

公开(公告)日：2012-05-22

申请号：US12829704

申请日：2010-07-02

Applicant: Chien-Ping Huang ,  Chih-Ming Huang ,  Han-Ping Pu ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

Inventor： Chien-Ping Huang ,  Chih-Ming Huang ,  Han-Ping Pu ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC: H01L21/00 ,  H01L21/46

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L23/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.

Abstract translation: 提供了堆叠半导体结构及其制造方法。 该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面， 经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板， 接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。 本发明防止回流引起的污染，备有特殊的模具，并消除闪光。

公开(公告)号：US20100267202A1

公开(公告)日：2010-10-21

申请号：US12829704

申请日：2010-07-02

Applicant: Chien-Ping Huang ,  Chih-Ming Huang ,  Han-Ping Pu ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

Inventor： Chien-Ping Huang ,  Chih-Ming Huang ,  Han-Ping Pu ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC: H01L21/50

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L23/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.

Abstract translation: 提供了堆叠半导体结构及其制造方法。 该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面， 经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板， 接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。 本发明防止回流引起的污染，备有特殊的模具，并消除闪光。

公开(公告)号：US07772685B2

公开(公告)日：2010-08-10

申请号：US11591974

申请日：2006-11-01

Applicant: Chien-Ping Huang ,  Chih-Ming Huang ,  Han-Ping Pu ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

Inventor： Chien-Ping Huang ,  Chih-Ming Huang ,  Han-Ping Pu ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC: H01L23/02

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L23/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.

Abstract translation: 提供了堆叠半导体结构及其制造方法。 该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面， 经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板， 接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。 本发明防止回流引起的污染，备有特殊的模具，并消除闪光。

公开(公告)号：US20080246142A1

公开(公告)日：2008-10-09

申请号：US12080798

申请日：2008-04-04

Applicant: Jeng-Yuan Lai ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

Inventor： Jeng-Yuan Lai ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC: H01L23/367

CPC classification number: H01L23/4334 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat section, and a heat dissipation section connected to the extension sections; and an encapsulant encapsulating the electronic component and the heat dissipation unit, wherein stress releasing sections are at least disposed at intersectional corners between the extension sections and the flat section so as to prevent projections from being formed by concentrated stresses in a punching process of the heat dissipation unit, thereby maintaining flatness of the flat section and further preventing circuits of the electronic component from being damaged due to a contact point produced between the electronic component and the flat section in a molding process.

Abstract translation: 公开了一种散热单元和具有该散热单元的半导体封装。 半导体封装包括载体; 电子部件，其安装在所述载体上并与其电连接; 散热单元，其包括附接到所述电子部件的平坦部分，连接到所述平坦部分的延伸部分和连接到所述延伸部分的散热部分; 以及封装电子部件和散热部的密封剂，其中应力释放部至少设置在延伸部和平坦部之间的交叉角处，以防止在热冲压加工中由于集中应力而形成突起 从而保持平坦部分的平坦度，并且进一步防止电子部件的电路在模制过程中由于在电子部件和平坦部分之间产生的接触点而损坏。

公开(公告)号：US20080160678A1

公开(公告)日：2008-07-03

申请号：US11657834

申请日：2007-01-24

Applicant: Yu-Po Wang ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

Inventor： Yu-Po Wang ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC: H01L21/60

CPC classification number: H01L23/49822 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package and a method for fabricating the same are proposed. A substrate having a first circuit layer, a second circuit layer, and a core layer formed between the first and second circuit layers is provided. At least one second opening is formed on the second circuit layer. At least one first opening is formed on the first circuit layer corresponding to the second opening. A plurality of finger holes corresponding to bond fingers on the first circuit layer are formed in the core layer. A through opening is formed in the core layer and communicates with the first and second openings. At least one chip is mounted on the first circuit layer and covers the first opening, with its active surface being exposed to the first opening. An encapsulant is formed to fill the first and second openings and the through opening and encapsulate the chip.

Abstract translation: 提出了一种半导体封装及其制造方法。 提供了具有形成在第一和第二电路层之间的第一电路层，第二电路层和芯层的衬底。 在第二电路层上形成至少一个第二开口。 在对应于第二开口的第一电路层上形成至少一个第一开口。 在芯层中形成与第一电路层上的接合指状对应的多个指孔。 在芯层中形成通孔，并与第一和第二开口连通。 至少一个芯片安装在第一电路层上并且覆盖第一开口，其有源表面暴露于第一开口。 形成密封剂以填充第一和第二开口和通孔并封装芯片。

公开(公告)号：US20070158861A1

公开(公告)日：2007-07-12

申请号：US11713362

申请日：2007-03-01

Applicant: Chien-Ping Huang ,  Yu-Po Wang

Inventor： Chien-Ping Huang ,  Yu-Po Wang

IPC: H01L23/28

CPC classification number: H01L24/10 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose ends are exposed. A plurality of conductive traces are formed on the dielectric layer and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings via which predetermined portions of the conductive traces are exposed and bonded to a plurality of solder balls. Thereby, positions of the bond pads are easily recognized and distinguished by the exposed ends of the conductive bumps, making the conductive traces capable of being well electrically connected through the conductive bumps to the bond pads to improve yield of the fabricated packages.

Abstract translation: 提供了一种形成在芯片上的积层的半导体封装以及半导体封装的制造方法。 在其接合焊盘上形成有多个导电凸块的芯片被容纳在载体的空腔内，并且介电层封装其端部露出的导电凸块。 多个导电迹线形成在电介质层上并与导电凸块的端部电连接。 焊接掩模层施加在导电迹线上并形成有开口，通过该开口，导电迹线的预定部分暴露并结合到多个焊球。 因此，接合焊盘的位置容易地被导电凸块的露出端识别和区分，使得导电迹线能够通过导电凸块与接合焊盘良好地电连接，以提高制造的封装的产量。

公开(公告)号：US07816187B2

公开(公告)日：2010-10-19

申请号：US12204066

申请日：2008-09-04

Applicant: Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L21/00

CPC classification number: H01L21/4832 ,  H01L21/4857 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract translation: 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US07423340B2

公开(公告)日：2008-09-09

申请号：US11112107

申请日：2005-04-21

Applicant: Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

Inventor： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC: H01L23/053 ,  H01L23/12 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28 ,  H01L23/02

CPC classification number: H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

公开(公告)号：US20080185726A1

公开(公告)日：2008-08-07

申请号：US12011906

申请日：2008-01-30

Applicant: Yu-Po Wang ,  Chien-Ping Huang ,  Wei-Chun Lin ,  Wen Cheng Lee

Inventor： Yu-Po Wang ,  Chien-Ping Huang ,  Wei-Chun Lin ,  Wen Cheng Lee

IPC: H01L23/49

CPC classification number: H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package substrate proposed by the invention includes a base body and a plurality of finger pads disposed on surface of the base body, wherein the finger pads are arranged in such a way that an angle is formed between connecting line of centers of two adjacent finger pads and the direction in which the finger pads are arranged. The finger pads are waterdrop shaped finger pads with arc ends and angle ends alternately disposed on surface of the substrate, alternately disposed waterdrop shaped finger pads and arc shaped finger pads, or alternately disposed arc shaped finger pads at a predetermined spacing. According to the present invention, distance between adjacent finger pads is reduced and problem of short circuit as a result of erroneous contact between bonding wire and adjacent finger pad is prevented.

Abstract translation: 本发明提出的半导体封装基板包括基体和设置在基体表面上的多个指垫，其中指垫以这样一种方式布置，使得两个相邻手指的中心的连接线之间形成一角度 垫和指垫的排列方向。 手指垫是具有弧端的水滴状指垫，并且角度端交替地设置在基板的表面上，交替地设置水滴形指状垫和弧形指状垫，或者以预定间隔交替布置的圆弧形指垫。 根据本发明，相邻指垫之间的距离减小，并且防止了接合线和相邻指垫之间的错误接触的结果导致的短路问题。