公开(公告)号：US07358140B2

公开(公告)日：2008-04-15

申请号：US11163968

申请日：2005-11-04

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L27/1052 ,  Y10S438/95

摘要： A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are added between two adjacent design normal regions of the M design normal regions, wherein N is a positive integer. Next, an actual structure is provided that includes (i) an actual substrate corresponding to the design substrate, (ii) a to-be-etched layer on the actual substrate, and (iii) a memory layer on the to-be-etched layer. Next, an edge printing process is performed on the memory layer so as to form (a) M normal memory portions aligned with the M design normal regions and (b) N sacrificial memory portions aligned with the N design sacrificial regions.

摘要翻译： 一种结构制造方法。 该方法包括提供一种设计结构，其包括（i）设计基板和（ii）设计基板上的M设计法线区域，其中M是大于1的正整数。接下来，在两个相邻设计之间添加N个设计牺牲区域 M正常区域的正常区域，其中N是正整数。 接下来，提供实际结构，其包括（i）与设计基板对应的实际基板，（ii）实际基板上的待蚀刻层，以及（iii）待蚀刻的存储层 层。 接下来，对存储层执行边缘打印处理，以便形成（a）与M设计法线区域对准的M个正常存储器部分和（b）与N个设计牺牲区域对准的N个牺牲存储器部分。

公开(公告)号：US07345370B2

公开(公告)日：2008-03-18

申请号：US10905590

申请日：2005-01-12

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L23/48

CPC分类号： H01L21/76885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76874 ,  H01L23/5283 ,  H01L23/53209 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.

摘要翻译： 使用图案结构（心轴）并激活结构的侧壁的方法形成导电侧壁间隔结构。 金属离子附着在结构的侧壁上，这些金属离子被还原成晶种。 然后对结构进行修整，并且种子材料被电镀以在结构的侧壁上形成布线。

公开(公告)号：US07265013B2

公开(公告)日：2007-09-04

申请号：US11162662

申请日：2005-09-19

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Kirk D. Peterson

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Kirk D. Peterson

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132

摘要： A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed on exposed-to-ambient surfaces of the structure. Then, portions of the conformal protective layer are removed so as to expose the capping region to the surrounding ambient without exposing the memory region to the surrounding ambient. Then, the capping region is removed so as to expose the positioning region to the surrounding ambient. Then, the positioning region is removed so as to expose the memory region to the surrounding ambient. Then, the memory region is directionally etched with remaining portions of the conformal protection layer serving as a blocking mask.

摘要翻译： 一种结构制造方法。 该方法包括提供一种结构，该结构包括：（a）待蚀刻层，（b）存储区域，（c）位于彼此顶部的定位区域（d）和封盖区域。 然后，定位区域缩进。 然后，在结构的暴露于环境的表面上形成保形层。 然后，去除保形层的一部分，以将覆盖区域暴露于周围环境，而不会使存储区域暴露于周围环境。 然后，去除封盖区域，以将定位区域暴露于周围环境。 然后，移除定位区域，以将存储区域暴露于周围环境。 然后，存储区域被定向蚀刻，保形层的剩余部分用作阻挡掩模。

公开(公告)号：US07176089B2

公开(公告)日：2007-02-13

申请号：US10853177

申请日：2004-05-26

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

IPC分类号： H01L21/336

CPC分类号： H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

摘要： A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

摘要翻译： 一种制造方法提供特别适用于高密度积分的垂直晶体管，其包括通过在沟槽中蚀刻或外延生长而形成的半导体柱的相对侧上的潜在独立栅极结构。 栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。 通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。 柱的上端由盖​​和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。 在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

公开(公告)号：US06940134B2

公开(公告)日：2005-09-06

申请号：US10064316

申请日：2002-07-02

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L29/76 ,  H01L27/088

CPC分类号： H01L21/76897 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/485 ,  H01L29/66545 ,  H01L2924/0002 ,  Y10S257/90 ,  H01L2924/00

摘要： Methods of forming a contact to a gate electrode or substrate despite misalignment of the contact opening due to lithographic techniques, and a semiconductor having such a contact. Silicide can be created on the gate and/or diffusion using the invention.

摘要翻译： 尽管由于平版印刷技术而导致接触开口的对准而形成与栅电极或基板的接触的方法，以及具有这种接触的半导体。 可以使用本发明在门和/或扩散上产生硅化物。

公开(公告)号：US06815737B2

公开(公告)日：2004-11-09

申请号：US10799819

申请日：2004-03-12

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L2710

CPC分类号： H01L21/76897 ,  H01L21/76888 ,  H01L21/76895

摘要： A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.

公开(公告)号：US06358813B1

公开(公告)日：2002-03-19

申请号：US09713766

申请日：2000-11-15

申请人： Steven J. Holmes ,  Charles Black ,  David J. Frank ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  William Hsioh-Lien Ma ,  Keith R. Milkove ,  Kathryn W. Guarini

发明人： Steven J. Holmes ,  Charles Black ,  David J. Frank ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  William Hsioh-Lien Ma ,  Keith R. Milkove ,  Kathryn W. Guarini

IPC分类号： H01L2120

CPC分类号： H01L28/92

摘要： Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

摘要翻译： 描述了通过在半导体介质上提供第一固态电极图案来增加半导体电容器的电容的方法，以有效增加所述第一电极图案的表面积的方式蚀刻所述第一电极图案上的地形特征， 所述电极图案上的电介质层基本上符合所述形貌特征，并且在所述电介质层上沉积第二固态电极图案，并且与所述第一固态电极图案充分绝缘，从而产生具有所述第一固态的电容 电极图案。

公开(公告)号：US06313492B1

公开(公告)日：2001-11-06

申请号：US09110487

申请日：1998-07-06

申请人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Ahmad D. Katnani ,  Niranjan M. Patel ,  Paul A. Rabidoux

发明人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Ahmad D. Katnani ,  Niranjan M. Patel ,  Paul A. Rabidoux

IPC分类号： H01L27108

CPC分类号： H01L28/82 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/039 ,  G03F7/095 ,  H01L21/0274 ,  H01L21/3085

摘要： A photoresist composition is disclosed having both negative tone and positive tone responses, giving rise to spaces being formed in the areas of diffraction which are exposed to intermediate amounts of radiation energy. This resist material may be used to print doughnut shapes or may be subjected to a second masking step, to print lines. Additionally, larger and smaller features may be obtained using a gray-scale filter in the reticle, to create larger areas of intermediate exposure areas.

摘要翻译： 公开了具有负色调和正色调响应的光致抗蚀剂组合物，在曝光到中等辐射能量的衍射区域中形成空间。 该抗蚀剂材料可以用于印刷圆环形状或者可以进行第二掩蔽步骤以打印线。 另外，可以使用掩模版中的灰度滤光片获得更大和更小的特征，以产生更大面积的中间曝光区域。

公开(公告)号：US06277543B1

公开(公告)日：2001-08-21

申请号：US09369412

申请日：1999-08-05

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： G03C500

CPC分类号： G03F7/70466 ,  G03F7/038 ,  G03F7/2022 ,  H01L21/0274

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art by providing a method to form unlinked features using hybrid resist. The method uses a trim process in order to trim the linking features from the “loops” formed by the hybrid resist. This allows the method to form a plurality of unlinked features rather than the loops. In order to trim the ends, a relatively larger trim area is formed adjacent the narrow feature line, either by a second exposure step or by utilizing a grey scale reticle. The broader or wider open area allows features to be formed in the narrow feature lines and being trimmed from the relatively large areas, thereby resulting in district features rather than loops.

摘要翻译： 本发明的优选实施例通过提供使用混合抗蚀剂形成不连接特征的方法来克服现有技术的局限性。 该方法使用修剪工艺来修剪由混合抗蚀剂形成的“环”的连接特征。 这允许该方法形成多个未链接的特征而不是循环。 为了修剪端部，通过第二曝光步骤或通过利用灰度光罩，形成与窄特征线相邻的相对较大的修整区域。 更宽或更宽的开放区域允许在窄特征线中形成特征并且从相对较大的区域修剪特征，从而导致区域特征而不是环。

公开(公告)号：US06271555B1

公开(公告)日：2001-08-07

申请号：US09052403

申请日：1998-03-31

申请人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Wendell P. Noble, Jr.

发明人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Wendell P. Noble, Jr.

IPC分类号： H01L27108

CPC分类号： H01L27/10873 ,  H01L27/10891 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S257/908

摘要： A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline. A bitline contact contacts the source/drain region and the insulating material surrounding the active wordline to thereby make the bitline contact borderless to the wordline. A fully encased passing wordline is also provided which is spaced from and insulated from the segment gate conductor and the active wordline.

摘要翻译： 公开了一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。 栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。 晶体管还具有具有源/漏区的单晶半导体衬底。 主动导电字线沉积在分段栅极导体的顶部并与其电接触，该字线是具有顶部和侧壁的导电材料。 电绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。 围绕有源字线的绝缘材料包括覆盖顶部并且围绕其侧壁的一部分的氮化硅，并且二氧化硅围绕有源字线的侧壁的其余部分。 位线触点接触源极/漏极区域和围绕有源字线的绝缘材料，从而使位线接触到字线。 还提供了完全封装的通过字线，其与分段栅极导体和有源字线间隔开并与之隔绝。