公开(公告)号：US09165896B2

公开(公告)日：2015-10-20

申请号：US14453969

申请日：2014-08-07

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hae Cheon Kim ,  Ho Kyun Ahn ,  Byoung Gue Min ,  Hyung Sup Yoon ,  Jong Won Lim

IPC: H01L33/00 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0225 ,  H01L2224/03466 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/1033 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1423 ,  H01L2924/201 ,  H01L2924/37001 ,  H01L2224/45099

Abstract: The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.

Abstract translation: 本发明涉及一种GaN晶体管及其制造方法，其中通过在源极，漏极和栅极的焊盘的边缘处形成欧姆金属层来改善焊盘的结构，因此 适于引线接合或背面通孔形成工艺。 因此，通过在制造GaN晶体管期间在焊盘的边缘处形成欧姆金属，可以增强焊盘的金属层与GaN基板之间的粘合力， 接合或背面通孔形成工艺，并提高器件的可靠性。

公开(公告)号：US12176306B2

公开(公告)日：2024-12-24

申请号：US17396258

申请日：2021-08-06

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sang Heung Lee ,  Soo Cheol Kang ,  Seong Il Kim ,  Hae Cheon Kim ,  Youn Sub Noh ,  Ho Kyun Ahn ,  Jong Won Lim ,  Sung Jae Chang ,  Hyun Wook Jung

IPC: H01L23/64 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205

Abstract: An apparatus and method for generating an electrical circuit of semiconductor channel resistor including a first passive element part including a resistor and a capacitor connected in parallel between a first port and a second port, and an ohmic resistor connected in series to the resistor and the capacitor which are connected in parallel are provided. The apparatus includes a substrate selection part configured to receive a selected substrate item; a resistor selection part configured to receive a selected resistor item; a capacitor selection part configured to receive a selected capacitor item; and a circuit generating part configured to generate an electrical circuit from the selected substrate item, the selected resistor item, and the selected capacitor item.

公开(公告)号：US09837719B2

公开(公告)日：2017-12-05

申请号：US15229891

申请日：2016-08-05

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Dong-Young Kim ,  Dong Min Kang ,  Seong-Il Kim ,  Hae Cheon Kim ,  Jae Won Do ,  Byoung-Gue Min ,  Ho Kyun Ahn ,  Hyung Sup Yoon ,  Sang-Heung Lee ,  Jong Min Lee ,  Jong-Won Lim ,  Yoo Jin Jang ,  Hyun Wook Jung ,  Kyu Jun Cho ,  Chull Won Ju

IPC: H01Q9/04 ,  H01Q1/50

CPC classification number: H01Q9/0407 ,  H01Q1/50 ,  H01Q9/0442

Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the multilayered substrate.

公开(公告)号：US08937002B2

公开(公告)日：2015-01-20

申请号：US14230031

申请日：2014-03-31

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Bum Bae ,  Eun Soo Nam ,  Jae Kyoung Mun ,  Sung Bock Kim ,  Hae Cheon Kim ,  Chull Won Ju ,  Sang Choon Ko ,  Jong-Won Lim ,  Ho Kyun Ahn ,  Woo Jin Chang ,  Young Rak Park

IPC: H01L21/20 ,  H01L29/66 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/088 ,  H01L21/02

CPC classification number: H01L29/66446 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0883

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract translation: 本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可通过再生技术在同一衬底上实现各种氮化物一体化结构（ 用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG） 。

公开(公告)号：US08841154B2

公开(公告)日：2014-09-23

申请号：US13916006

申请日：2013-06-12

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hyung Sup Yoon ,  Byoung-Gue Min ,  Jong-Won Lim ,  Ho Kyun Ahn ,  Jong Min Lee ,  Seong-il Kim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L21/00 ,  H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/66863

Abstract: Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced. The method of manufacturing a field effect type compound semiconductor device includes: stacking an active layer and an ohmic layer on a substrate and forming a first oxide layer on the ohmic layer; forming a mesa region in predetermined regions of the first oxide layer, the ohmic layer, and the active layer; planarizing the mesa region after forming a nitride layer by evaporating a nitride on the mesa region; forming an ohmic electrode on the first oxide layer; forming a minute gate resist pattern after forming a second oxide layer on a semiconductor substrate in which the ohmic electrode is formed and forming a minute gate pattern having a under-cut shaped profile by dry-etching the first oxide layer, the nitride layer, and the second oxide layer; forming a gate recess region by forming a head pattern of a gamma gate electrode on the semiconductor substrate; and forming the gamma gate electrode by evaporating refractory metal on the semiconductor substrate in which the gate recess region is formed.

Abstract translation: 公开了一种制造场效应型化合物半导体器件的方法，其中器件的漏电流降低并且击穿电压增强。 制造场效应型化合物半导体器件的方法包括：在衬底上堆叠有源层和欧姆层，并在欧姆层上形成第一氧化物层; 在所述第一氧化物层，所述欧姆层和所述有源层的预定区域中形成台面区域; 通过在台面区域上蒸发氮化物，在形成氮化物层之后使台面区域平坦化; 在所述第一氧化物层上形成欧姆电极; 在形成欧姆电极的半导体衬底上形成第二氧化物层之后形成微小栅极抗蚀剂图案，并通过干蚀刻第一氧化物层，氮化物层和形成具有下切形状轮廓的微小栅极图案 第二氧化物层; 通过在所述半导体衬底上形成伽马栅电极的头部图形来形成栅极凹部区域; 以及通过在形成有所述栅极凹部的所述半导体衬底上蒸发难熔金属而形成所述γ栅电极。

公开(公告)号：US20140017885A1

公开(公告)日：2014-01-16

申请号：US13916006

申请日：2013-06-12

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hyung Sup YOON ,  Byoung-gue Min ,  Jong-Won Lim ,  Ho Kyun Ahn ,  Jong Min Lee ,  Seong-il Kim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/66863

Abstract: Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced. The method of manufacturing a field effect type compound semiconductor device includes: stacking an active layer and an ohmic layer on a substrate and forming a first oxide layer on the ohmic layer; forming a mesa region in predetermined regions of the first oxide layer, the ohmic layer, and the active layer; planarizing the mesa region after forming a nitride layer by evaporating a nitride on the mesa region; forming an ohmic electrode on the first oxide layer; forming a minute gate resist pattern after forming a second oxide layer on a semiconductor substrate in which the ohmic electrode is formed and forming a minute gate pattern having a under-cut shaped profile by dry-etching the first oxide layer, the nitride layer, and the second oxide layer; forming a gate recess region by forming a head pattern of a gamma gate electrode on the semiconductor substrate; and forming the gamma gate electrode by evaporating refractory metal on the semiconductor substrate in which the gate recess region is formed.

Abstract translation: 公开了一种制造场效应型化合物半导体器件的方法，其中器件的漏电流降低并且击穿电压增强。 制造场效应型化合物半导体器件的方法包括：在衬底上堆叠有源层和欧姆层，并在欧姆层上形成第一氧化物层; 在所述第一氧化物层，所述欧姆层和所述有源层的预定区域中形成台面区域; 通过在台面区域上蒸发氮化物，在形成氮化物层之后使台面区域平坦化; 在所述第一氧化物层上形成欧姆电极; 在形成欧姆电极的半导体衬底上形成第二氧化物层之后形成微小栅极抗蚀剂图案，并通过干蚀刻第一氧化物层，氮化物层和形成具有下切形状轮廓的微小栅极图案 第二氧化物层; 通过在所述半导体衬底上形成伽马栅电极的头部图形来形成栅极凹部区域; 以及通过在形成有所述栅极凹部的所述半导体衬底上蒸发难熔金属而形成所述γ栅电极。