公开(公告)号：US09881695B2

公开(公告)日：2018-01-30

申请号：US15356223

申请日：2016-11-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G06F7/02 ,  H03M13/00 ,  G11C29/50 ,  G11C11/16 ,  G06F11/08 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

公开(公告)号：US09870812B2

公开(公告)日：2018-01-16

申请号：US15370114

申请日：2016-12-06

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Halbert S. Lin

IPC: G11C7/00 ,  G11C11/16 ,  G11C7/12 ,  G11C7/10 ,  G11C7/22 ,  G06F12/0802 ,  G11C11/4076

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

公开(公告)号：US09691442B2

公开(公告)日：2017-06-27

申请号：US14667888

申请日：2015-03-25

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Dietmar Gogl

IPC: G11C7/02 ,  G11C5/14 ,  G11C16/12 ,  G11C16/30 ,  G11C7/06 ,  G11C8/12 ,  G11C7/18 ,  G11C7/10

CPC classification number: G11C7/02 ,  G11C5/14 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C16/12 ,  G11C16/30

Abstract: In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.

公开(公告)号：US20170178709A1

公开(公告)日：2017-06-22

申请号：US15452831

申请日：2017-03-08

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0806 ,  G06F12/0879 ,  G06F2212/62 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/22 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/5607 ,  Y02D10/13

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.

公开(公告)号：US20170117029A1

公开(公告)日：2017-04-27

申请号：US15401235

申请日：2017-01-09

Applicant: Everspin Technologies, Inc.

Inventor： Jason Janesky ,  Syed M. Alam ,  Dimitri Houssameddine ,  Mark Deherrera

IPC: G11C11/16 ,  G11C29/12 ,  G11C17/16

CPC classification number: G11C11/1673 ,  G11C11/16 ,  G11C11/1675 ,  G11C17/16 ,  G11C29/021 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/12 ,  G11C29/50

Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.

公开(公告)号：US20170104498A1

公开(公告)日：2017-04-13

申请号：US15385130

申请日：2016-12-20

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: H03M13/29 ,  G06F11/10

CPC classification number: H03M13/2906 ,  G06F11/1012 ,  G06F11/1076

Abstract: In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.

公开(公告)号：US09502093B2

公开(公告)日：2016-11-22

申请号：US15167758

申请日：2016-05-27

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Matthew R. Croft ,  Chitra Subramanian ,  Halbert Lin

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/00 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0076 ,  G11C2029/0411

Abstract: A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits using an additional offset current, and compare the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time.

Abstract translation: 自旋转矩磁阻存储器包括耦合到磁头阵列的阵列读取电路和阵列写入电路。 阵列读取电路对阵列中的磁头进行采样，向磁头施加写入电流脉冲以将其设置为第一逻辑状态，使用附加的偏移电流对磁性位进行重新采样，并比较采样和重采样的结果，以确定 每个磁头的位状态。 对于具有第二逻辑状态的页面中的每个磁性位，阵列写入电路启动回写，其中写回包括施加与第一写入电流脉冲相比具有相反极性的第二写入电流脉冲以设置 磁头到第二个状态。 在写回开始之后可以接收读取或写入操作，其中在写入操作的情况下可以中止一部分位的写回。 可以执行回写，使得磁头的不同部分在不同的时间被写回，从而及时地交错回写电流脉冲。

公开(公告)号：US09378796B2

公开(公告)日：2016-06-28

申请号：US14580379

申请日：2014-12-23

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/15

CPC classification number: G11C11/1675 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673

Abstract: A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied.

Abstract translation: 向磁性隧道结装置施加写入电流的方法使得亚阈值泄漏最小化。 NMOS和PMOS跟随器电路用于施加写入电流，并且在施加写入电流之前，跟随器电路的偏置信号与全局偏置信号隔离。

公开(公告)号：US20160099039A1

公开(公告)日：2016-04-07

申请号：US14970563

申请日：2015-12-16

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Matthew R. Croft ,  Chitra Subramanian ,  Halbert Lin

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/00 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0076 ,  G11C2029/0411

Abstract: A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling.

Abstract translation: 自旋转矩磁阻存储器包括耦合到磁头阵列的阵列读取电路和阵列写入电路。 阵列读取电路对阵列中的磁头进行采样，向磁头施加写入电流脉冲以将其设置为第一逻辑状态，对磁头进行重新采样，并比较采样和重采样的结果，以确定每个磁性的位状态 位。 对于具有第二逻辑状态的页面中的每个磁性位，阵列写入电路启动回写，其中写回包括施加与第一写入电流脉冲相比具有相反极性的第二写入电流脉冲以设置 磁头到第二个状态。 在写回开始之后可以接收读取或写入操作，其中在写入操作的情况下可以中止一部分位的写回。 可以执行回写，使得磁头的不同部分在不同的时间被写回，从而及时地交错回写电流脉冲。 在重采样期间也可以使用偏移电流。

公开(公告)号：US20160093349A1

公开(公告)日：2016-03-31

申请号：US14502367

申请日：2014-09-30

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Dimitri Houssameddine ,  Syed M. Alam ,  Jon Slaughter ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0804 ,  G11C11/1677 ,  Y02D10/13

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

Abstract translation: 存储器设备被配置为识别要从第一状态改变到第二状态的位单元的集合。 在一些示例中，存储器件可以向该位单元集合施加第一电压以将位组中的至少第一部分改变为第二状态。 在一些情况下，存储器件还可以识别在应用第一电压之后保持在第一状态的位单元的第二部分。 在这些情况下，存储器件可以将具有更大幅度，持续时间或两者的第二电压施加到位单元集合的第二部分，以便将位单元的第二部分设置为第二状态。