公开(公告)号：US5687121A

公开(公告)日：1997-11-11

申请号：US645630

申请日：1996-05-14

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

IPC分类号： G11C8/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C16/00

CPC分类号： G11C8/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5642 ,  G11C2216/20 ,  G11C8/00

摘要： A flash memory wordline decoder includes a plurality of voltage terminals to receive a plurality of voltages, a plurality of address terminals to receive a plurality of address signals, a procedure terminal to receive a procedure signal, and a plurality of output wordlines adapted to be coupled to a bank of flash transistors. The wordline decoder circuit is configured to decode the address signals and includes latches coupled to the wordlines, where the latches are configured to latch the wordlines and to provide an operational voltage on the wordline to accomplish a predetermined operation responsive to the procedure signal. Advantages of the invention include a verification with a low verification voltage such as 1 V or less for operating with a VDD supply voltage as low as 1.5 V. The decoder also reduces erase/write cycle time and improves expected lifetime of the flash memory due to reduced stress on the flash transistors within the flash memory.

摘要翻译： 闪存字线解码器包括多个用于接收多个电压的电压端子，多个地址端子以接收多个地址信号，用于接收过程信号的过程终端，以及适于耦合的多个输出字线 到一组闪存晶体管。 字线解码器电路被配置为对地址信号进行解码并且包括耦合到字线的锁存器，其中锁存器被配置为锁存字线并且在字线上提供操作电压以响应于过程信号来完成预定操作。 本发明的优点包括使用诸如1V或更低的验证电压的验证，用于以低至1.5V的VDD电源电压工作。解码器还减少了擦除/写入周期时间并且改善了闪存的预期寿命，这是由于 闪存中的闪存晶体管的应力减小。

公开(公告)号：US20110170357A1

公开(公告)日：2011-07-14

申请号：US13072281

申请日：2011-03-25

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

摘要翻译： 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

公开(公告)号：US07289366B2

公开(公告)日：2007-10-30

申请号：US11376076

申请日：2006-03-15

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

公开(公告)号：US06850438B2

公开(公告)日：2005-02-01

申请号：US10351179

申请日：2003-01-24

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

IPC分类号： G11C16/04 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3445 ,  G11C2216/18 ,  G11C2216/22 ,  H01L27/11521 ,  H01L27/11524

摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

公开(公告)号：US06788612B2

公开(公告)日：2004-09-07

申请号：US10423559

申请日：2003-04-25

申请人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

发明人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

IPC分类号： G11C800

CPC分类号： G11C16/10 ,  G11C7/18 ,  G11C8/12 ,  G11C2216/22

摘要： In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

公开(公告)号：US06620682B1

公开(公告)日：2003-09-16

申请号：US09978230

申请日：2001-10-16

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

IPC分类号： H01L21336

CPC分类号： G11C16/3404 ,  G11C16/0416 ,  G11C16/344 ,  H01L27/115 ,  H01L29/66825

摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

摘要翻译： 在本发明中，示出了在NOR型EEPROM闪速存储器阵列的存储单元操作中使用三个并行字线电压的方法。 第一并行字线电压控制在所选择的存储器块内的选定字线上的操作。 第二并发字线电压抑制所选存储块中未选择的字线上的单元，并且第三并发字线电压抑制未被选择的块中的未选择的单元从干扰条件。 此外，三个连续的字线电压允许块被擦除，块内的页被擦除，并且块内的页被禁止进一步擦除。 三个连续的电压还允许检测电池的过度擦除，基于页面的校正，以及验证校正的单元的阈值电压是否高于擦除值但低于擦除值。 本文描述的方法产生具有窄电压分布的电池阈值电压。

公开(公告)号：US06556481B1

公开(公告)日：2003-04-29

申请号：US09852247

申请日：2001-05-09

申请人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee ,  Mervyn Wong

发明人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee ,  Mervyn Wong

IPC分类号： G11C1604

CPC分类号： G11C16/10 ,  G11C2216/28

摘要： In the present invention a three step write of a nonvolatile single transistor cell is disclosed. The three steps comprise erasing, reverse programming and programming which can be applied to a plurality of cell types to produce a symmetrical design and allowing shrinkage of the cell beyond that which is possible with other cells designed to use a two step write procedure. The methodology can be applied to either N-channel or P-channel devices and can be used on various type memory cells such as “ETOX”, “NOR” type, “AND” type, and “OR” type. Erasing and programming steps increase the Vt of the cell transistor, whereas reverse programming decreases the Vt of the cell transistor. Over-erase problems are eliminated using the three step write procedure.

摘要翻译： 在本发明中，公开了一种非易失性单晶体管单元的三步写入。 三个步骤包括擦除，反向编程和编程，其可以应用于多个单元类型以产生对称设计，并且允许单元的收缩超过设计为使用两步写入过程的其他单元可能的缩小。 该方法可应用于N沟道或P沟道器件，可用于各种类型的存储单元，例如“ETOX”，“NOR”型，“AND”型和“OR”型。 擦除和编程步骤增加了单元晶体管的Vt，而反向编程减小了单元晶体管的Vt。 使用三步写入过程可以消除过度擦除问题。

公开(公告)号：US06181607B2

公开(公告)日：2001-01-30

申请号：US09351740

申请日：1999-07-12

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C1604

CPC分类号： G11C16/0425

摘要： In the present invention an array for a reverse split gate device is described for creating a flash memory that avoids both programming and erase disturb conditions. The device is designed so that the stacked gate is associated with the source and the enhancement gate is associated with the drain. This is the reverse of a conventional spit gate design and allows the drain to buffer the stacked gate from bit lines of a flash memory array. The source line now key to both program and erase operations is laid out in rows where two adjacent rows of cells share the same source line. The source line can be segmented to prevent the entire length of the pair of rows from being erased. The cell is programmed by flowing current backwards in the channel and injecting electrons into the floating gate from an impact ionization that occurs near the source. Erasure is accomplished by Fowler-Nordheim tunneling from the floating gate to the source caused by a potential between the source and the enhancement gate.

摘要翻译： 在本发明中，描述了一种用于产生一个避免编程和擦除干扰条件的闪速存储器的用于反向分离栅极器件的阵列。 设备被设计成使得堆叠的栅极与源相关联，并且增强栅极与漏极相关联。 这与传统的喷口设计相反，并允许漏极从闪存阵列的位线缓冲堆叠的栅极。 现在，编程和擦除操作的关键是将两行的单元格共享相同的源行。 可以对源极线进行分段，以防止该对行的整个长度被擦除。 通过在通道中向后流动电流并将电子从在源附近发生的冲击电离注入到浮动栅极中来编程单元。 通过Fowler-Nordheim从源极和增强门之间的电位引起的浮动栅极到源极的擦除来完成擦除。

公开(公告)号：US5920503A

公开(公告)日：1999-07-06

申请号：US850489

申请日：1997-05-02

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C11/56 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  G11C16/00

CPC分类号： G11C16/3427 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3418 ,  G11C16/3431 ,  G11C2211/5642 ,  G11C2216/20 ,  G11C8/00

摘要： A flash memory with a novel bitline and sourceline decoder includes a first bank of flash transistors forming a plurality of rows and a plurality of columns, and having wordlines, bitlines and a first sourceline. A second bank of flash transistors forms a plurality of rows and a plurality of columns, and has wordlines, bitlines and a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline. A bitline and sourceline decoder is coupled to the bitlines and sourcelines and configured to receive a bitline address signal and to decode the bitline address signal to select predetermined bitlines and sourcelines. The bitline and sourceline decoder includes a latch coupled to the bitlines, the first sourceline and the second sourceline and configured to latch selected bitlines and sourcelines to selectively provide erase voltages on the selected bitlines and sourcelines. As a result of the novel memory architecture, a flexible number of bytes can be selected for erasure. The selected number of bytes can range from one byte to 64K bytes or more. Advantages of the invention include reduced erase/write cycle time and an improved expected lifetime of the flash memory due to reduced stress on the flash transistors within the flash memory.

摘要翻译： 具有新颖位线和源线解码器的闪速存储器包括形成多行和多列的第一闪存晶体组，并具有字线，位线和第一源极线。 闪存晶体管的第二组形成多个行和多个列，并且具有字线，位线和第二源极线。 字线解码器耦合到字线并且被配置为接收字线地址信号并解码字线地址信号以选择字线。 位线和源线解码器耦合到位线和源极线，并被配置为接收位线地址信号并解码位线地址信号以选择预定的位线和源线。 位线和源线解码器包括耦合到位线的锁存器，第一源极线路和第二源极线路，并且被配置为锁存所选择的位线和源极线以选择性地在所选择的位线和源极线上提供擦除电压。 作为新颖的存储器架构的结果，可以选择灵活的字节数来进行擦除。 所选字节数可以从一个字节到64K字节或更多。 由于闪速存储器内的闪存晶体管上的应力减小，本发明的优点包括减少的擦除/写入周期时间和闪存的预期寿命的改善。

公开(公告)号：US5917757A

公开(公告)日：1999-06-29

申请号：US882558

申请日：1997-06-25

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G05F3/20 ,  G11C5/14 ,  G11C8/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/34 ,  H01L27/115 ,  H02M3/07 ,  H03K3/0231 ,  G11C7/00

CPC分类号： G11C16/3427 ,  G05F3/20 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3445 ,  G11C5/145 ,  G11C8/10 ,  H01L27/115 ,  H02M3/073 ,  H03K3/0231 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5645 ,  G11C2216/18 ,  G11C8/00 ,  G11C8/14

摘要： A flash memory with a high speed erasing structure includes a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline. A wordline decoder is coupled to the wordlines and configured to selectively apply voltages to the wordlines to perform procedures on the flash transistors, where the procedures include a read procedure, an erase procedure and a program procedure. During the erase procedure, the wordline decoder is configured to apply a first increasingly negative voltage in a first voltage range to at least one selected wordline until a first threshold voltage is met, then to apply a second increasingly negative voltage in a second voltage range to the selected wordline and to simultaneously apply a third negative voltage in a third voltage range to at least one deselected wordline. Another embodiment of the invention increases the selected sourceline voltage to achieve a high voltage differential between the gate and source of flash transistors selected to be erased. Advantages of the invention include a fast erasing procedure due to the increased voltage differential applied between the gate and source of flash transistors selected to be erased. Moreover, since the deselected wordlines are also ramped to a negative voltage, stress is reduced on the deselected wordline drivers, thereby increasing the longevity of the flash memory.

摘要翻译： 具有高速擦除结构的闪速存储器包括具有多个字线的组闪存晶体管，多个位线和源极线。 字线解码器耦合到字线并且被配置为选择性地向字线施加电压以对闪存晶体管执行过程，其中过程包括读取过程，擦除过程和程序过程。 在擦除过程期间，字线解码器被配置为将第一电压范围中的第一越来越大的负电压施加到至少一个选定字线，直到满足第一阈值电压，然后在第二电压范围内施加第二越来越大的负电压， 并且将第三电压范围中的第三负电压同时施加到至少一个取消选择的字线。 本发明的另一实施例增加了所选择的源极线电压，以实现选择被擦除的闪光晶体管的栅极和源极之间的高电压差。 本发明的优点包括快速擦除程序，这是由于在被选择被擦除的闪光晶体管的栅极和源极之间施加的电压差增大。 此外，由于取消选择的字线也被斜变为负电压，所以在取消选择的字线驱动器上的应力减小，从而增加了闪存的使用寿命。