公开(公告)号：US20190043734A1

公开(公告)日：2019-02-07

申请号：US15668502

申请日：2017-08-03

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/31 ,  H01L23/28

Abstract: An electronics package includes an insulating substrate, an electrical component having an active surface coupled to a first surface of the insulating substrate, and an insulating structure disposed adjacent the electrical component on the first surface of the insulating substrate. A first wiring layer is formed on a top surface of the insulating structure and extends down at least one sloped side surface of the insulating structure. A second wiring layer is formed on a second surface of the insulating substrate. The second wiring layer extends through a plurality of vias in the insulating substrate to electrically couple at least one contact pad on the active surface of the electrical component to the first wiring layer.

公开(公告)号：US09846218B2

公开(公告)日：2017-12-19

申请号：US13731388

申请日：2012-12-31

Applicant: General Electric Company

Inventor： William Hullinger Huber ,  Bahman E. Kashef ,  Kaustubh Ravindra Nagarkar

IPC: G01R35/00 ,  G06F17/11 ,  A61B5/06 ,  A61B5/00

CPC classification number: G01R35/00 ,  A61B5/062 ,  A61B5/6852 ,  A61B2560/0223

Abstract: A position and orientation system and method is provided. A magnetoresistance sensor is provided having a sensor array configured to measure magnetic fields and a metallic coil positioned within the magnetoresistance sensor. In certain embodiments, the magnetic coil may be used to generate a known magnetic field that, when measured by the sensor array, may be used to determine or update a calibration constant for the system.

公开(公告)号：US20160146556A1

公开(公告)日：2016-05-26

申请号：US14549268

申请日：2014-11-20

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Kaustubh Ravindra Nagarkar ,  Matthew Jeremiah Misner ,  Faisal Razi Ahmad

IPC: F28F21/02 ,  F28F21/06

CPC classification number: F28F21/02 ,  B22F1/0018 ,  B22F3/11 ,  B22F3/1115 ,  B22F3/1137 ,  B22F3/114 ,  B22F3/24 ,  B22F7/00 ,  B22F7/02 ,  B22F2001/0037 ,  B22F2998/10 ,  F28F13/003 ,  F28F21/00 ,  F28F21/067 ,  F28F2255/18 ,  H01L23/3733 ,  Y10T428/249955 ,  Y10T428/249958 ,  Y10T428/249978 ,  B22F3/10 ,  B22F2003/244 ,  B22F3/26 ,  B22F2007/045

Abstract: Composite foams are provided including a metal template and a conformal atomic-scale film disposed over such metal template to form a 3-dimensional interconnected structure. The metal template includes a plurality of sintered interconnects, having a plurality of first non-spherical pores, a first non-spherical porosity, and a first surface-area-to-volume ratio. The conformal atomic-scale film has a plurality of second non-spherical pores, a second non-spherical porosity, and a second surface-area-to-volume ratio approximately equal to the first surface-area-to-volume ratio. The plurality of sintered interconnects has a plurality of dendritic particles and the conformal atomic-scale film includes at least one of a layer of graphene and a layer of hexagonal boron nitride.

Abstract translation: 提供了复合泡沫，其包括设置在这种金属模板上的金属模板和保形原子级膜以形成3维互连结构。 金属模板包括具有多个第一非球形孔，多个第一非球形孔隙和第一表面积与体积比的多个烧结互连。 保形原子级膜具有多个第二非球形孔，第二非球形孔隙率和大约等于第一表面积体积比的第二表面积体积比。 多个烧结互连具有多个树枝状颗粒，并且共形原子尺度膜包括石墨烯层和六方氮化硼层中的至少一个。

公开(公告)号：US10541153B2

公开(公告)日：2020-01-21

申请号：US15668468

申请日：2017-08-03

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/28 ,  H01L23/31

Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.

公开(公告)号：US20190157227A1

公开(公告)日：2019-05-23

申请号：US15816360

申请日：2017-11-17

Applicant: General Electric Company

Inventor： Raymond Albert Fillion ,  Kaustubh Ravindra Nagarkar

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10 ,  H01L25/065 ,  H01L23/50

Abstract: A reconfigured semiconductor logic device includes a semiconductor logic device comprising a plurality of input/output (I/O) pads formed on an active surface thereof and a redistribution layer. The redistribution layer comprises an insulating layer formed atop the active surface of the semiconductor logic device such that the insulating layer does not extend beyond an outer perimeter of the active surface and a patterned conductive wiring layer positioned above the insulating layer. The patterned conductive wiring layer includes a plurality of terminal buses formed on a top surface of the insulating layer. Each terminal bus of the plurality of terminal buses is electrically coupled to multiple I/O pads of the plurality of I/O pads through vias formed in the insulating layer.

公开(公告)号：US10211141B1

公开(公告)日：2019-02-19

申请号：US15816254

申请日：2017-11-17

Applicant: General Electric Company

Inventor： Raymond Albert Fillion ,  Kaustubh Ravindra Nagarkar

IPC: H01L23/49 ,  H01L23/498 ,  H01L27/118 ,  H01L23/00 ,  H01L21/768

Abstract: An embedded semiconductor package includes a semiconductor logic device comprising a plurality of signal input/output (I/O) pads spaced at a first pitch on an active surface thereof and a plurality of power I/O pads and ground I/O pads spaced on the active surface at a second pitch larger than the first pitch. At least one interconnect layer overlies the semiconductor logic device. Each of the at least one interconnect layers includes an insulating layer and a conductive layer formed on the insulating layer and extending into a plurality of vias formed therethrough. The conductive layer is electrically coupled to the plurality of signal I/O pads and the plurality of power I/O pads and ground I/O pads.

公开(公告)号：US20190043794A1

公开(公告)日：2019-02-07

申请号：US15668522

申请日：2017-08-03

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar ,  Raymond Albert Fillion

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: An electronics package includes a support substrate, an electrical component having an active surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and at least one side wall of the electrical component. A functional layer comprising at least one functional component is formed on at least one of a sloped side wall of the insulating structure and a backside surface of the electrical component. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is electrically coupled to the functional layer through at least one via in the support substrate.

公开(公告)号：US10163773B1

公开(公告)日：2018-12-25

申请号：US15675144

申请日：2017-08-11

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Kaustubh Ravindra Nagarkar ,  Arun Virupaksha Gowda ,  James Wilson Rose

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.

公开(公告)号：US20180160929A1

公开(公告)日：2018-06-14

申请号：US15377696

申请日：2016-12-13

Applicant: General Electric Company ,  Brigham Young University

Inventor： Jeffrey M. Ashe ,  Kaustubh Ravindra Nagarkar ,  Christopher Michael Puleo ,  Christopher Fred Keimel ,  Craig Patrick Galligan ,  Yizhen Lin ,  Nancy Cecelia Stoffel ,  Richard Vanfleet ,  Robert Davis ,  Guohai Chen

IPC: A61B5/0478 ,  A61B5/1473 ,  A61B5/145 ,  A61B5/11 ,  A61B7/02 ,  A61N1/05

CPC classification number: A61B5/0478 ,  A61B5/11 ,  A61B5/14546 ,  A61B5/1473 ,  A61B7/023 ,  A61B2017/0023 ,  A61B2017/00911 ,  A61B2562/0209 ,  A61B2562/0285 ,  A61B2562/06 ,  A61B2562/125 ,  A61N1/0531 ,  A61N1/0534

Abstract: The present approach relates to the fabrication and use of a probe array having multiple individual probes. In one embodiment, the probes of the probe array may be functionalized such that certain of the probes are suitable for electrical sensing (e.g., recording) or stimulation, non-electrical sensing or stimulation (e.g., chemical sensing and/or release of biomolecules when activated), or a combination of electrical and non-electrical sensing or stimulation.

公开(公告)号：US20180020548A1

公开(公告)日：2018-01-18

申请号：US15209244

申请日：2016-07-13

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Kaustubh Ravindra Nagarkar

IPC: H05K1/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H05K3/32 ,  H01L23/00 ,  H05K1/02 ,  H01L21/48 ,  H01M10/0585 ,  H05K3/40 ,  H01L21/56 ,  H05K1/11

CPC classification number: H05K1/185 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/58 ,  H01L23/66 ,  H01L24/00 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/83 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/1421 ,  H01L2924/1461 ,  H01M2/20 ,  H01M6/40 ,  H01M10/0436 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/0585 ,  H01M10/0587 ,  H01M10/425 ,  H01M2220/30 ,  H04W4/70 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/32 ,  H05K3/4038 ,  H05K2201/10037 ,  H05K2201/10098 ,  H05K2201/10151 ,  H05K2203/1316 ,  H05K2203/1327

Abstract: A system and method for providing a packaged electronics module having a dry film battery incorporated therein is disclosed. The packaged electronics module includes a first dielectric layer, at least one electronic component attached to or embedded in the first dielectric layer, a dry film battery formed on the first dielectric layer, and metal interconnects mechanically and electrically coupled to the at least one electronic component and the dry film battery to form electrical interconnections thereto. Electronic components in the form of a MEMS type sensor, semiconductor device and communications device may be included in the module along with the battery to provide a self-powered module capable of communicating with other like packaged electronics modules.