公开(公告)号：US10340369B2

公开(公告)日：2019-07-02

申请号：US15703484

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/417 ,  H01L29/267

Abstract: A tunneling field effect transistor device disclosed herein includes a substrate, a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above the substrate, and a second semiconductor material positioned above at least a portion of the gate region and above the source region. The first semiconductor material is part of the drain region, and the second semiconductor material defines the channel region. The device also includes a third semiconductor material positioned above the second semiconductor material and above at least a portion of the gate region and above the source region. The third semiconductor material is part of the source region, and is doped with a second type of dopant material that is opposite to the first type of dopant material. A gate structure is positioned above the first, second and third semiconductor materials in the gate region.

公开(公告)号：US10020395B2

公开(公告)日：2018-07-10

申请号：US14853012

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/7827 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66666 ,  H01L29/78

Abstract: One illustrative method disclosed herein includes, among other things, forming a trench in a semiconductor substrate, forming a liner semiconductor material above the entire interior surface of the trench, the liner semiconductor material defining a transistor cavity, forming a gate structure that is at least partially positioned within the transistor cavity, and performing at least one epitaxial deposition process to form a source region structure and a drain region structure on opposite sides of the gate structure, wherein at least a portion of each of the source region structure and the drain region structure is positioned within the transistor cavity.

公开(公告)号：US09558943B1

公开(公告)日：2017-01-31

申请号：US14797531

申请日：2015-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak

IPC: H01L21/02 ,  H01L21/321 ,  H01L29/06 ,  H01L29/201 ,  H01L29/161

CPC classification number: H01L21/0265 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02645 ,  H01L21/3212 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/201

Abstract: A method of forming a stress relaxed buffer layer (SRB) on a textured or grooved silicon (Si) surface and the resulting device are provided. Embodiments include forming a textured surface in an upper surface of a Si wafer; epitaxially growing a low-temperature seed layer on the textured surface of the Si wafer; depositing a SRB layer over the low-temperature seed layer; and planarizing an upper surface of the SRB layer.

Abstract translation: 提供了在纹理或开槽的硅（Si）表面上形成应力松弛缓冲层（SRB）的方法，并且提供了所得到的器件。 实施例包括在Si晶片的上表面中形成纹理表面; 在Si晶片的织构化表面上外延生长低温种子层; 在低温种子层上沉积SRB层; 并平坦化SRB层的上表面。

公开(公告)号：US20160133740A1

公开(公告)日：2016-05-12

申请号：US14983217

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak ,  Behtash Behin-Aein ,  Mehdi Salmani-Jelodar

IPC: H01L29/78 ,  H01L29/201 ,  H01L29/10 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/66795 ,  H01L29/6681

Abstract: One illustrative device disclosed herein includes, among other things, a substrate made of a first semiconductor material, at least one layer of insulating material positioned above the substrate, a fin structure positioned above the layer of insulating material and the substrate, the fin structure comprising first, second and third layers of semiconductor material, wherein the semiconductor materials of the first, second and third layers are different than the first semiconductor material, and a gate structure around a portion of the fin structure comprised of the first, second and third layers of semiconductor material.

公开(公告)号：US08716156B1

公开(公告)日：2014-05-06

申请号：US13757069

申请日：2013-02-01

Applicant: GlobalFoundries Inc.

Inventor： Bartlomiej Jan Pawlak ,  Steven Bentley ,  Ajey Jacob

IPC: H01L21/31

CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes forming a mandrel structure above a semiconductor substrate, performing an oxidation process to oxidize at least a portion of the mandrel structure so as to thereby define oxidized regions on the mandrel structure, removing the oxidized regions to thereby defined a reduced thickness mandrel structure, forming a plurality of fins on the reduced thickness mandrel structure and performing an etching process to selectively remove at least a portion of the reduced thickness mandrel structure so as to thereby expose at least a portion of each of the fins.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成心轴结构，执行氧化过程以氧化心轴结构的至少一部分，从而在心轴结构上限定氧化区，去除氧化区，由此限定减少 厚度心轴结构，在厚度较小的心轴结构上形成多个翅片，并执行蚀刻工艺以选择性地移除至少一部分厚度较小的心轴结构，从而露出每个翅片的至少一部分。

公开(公告)号：US09793384B2

公开(公告)日：2017-10-17

申请号：US14503587

申请日：2014-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66977 ,  H01L21/823418 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/66356 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/7827 ,  H01L29/7848

Abstract: One illustrative method of forming a TFET device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device, masking the drain region while exposing at least a portion of the gate region and exposing the source region, forming a second semiconductor material above the gate region and above the source region, forming a third semiconductor material above the second semiconductor material and above the gate region and above the source region, the third semiconductor material being doped with an opposite type of dopant material than in the first semiconductor material, masking the drain region, and forming a gate structure above at least a portion of the exposed gate region.

公开(公告)号：US09741847B2

公开(公告)日：2017-08-22

申请号：US14953874

申请日：2015-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/761 ,  H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L21/265

CPC classification number: H01L29/7827 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/0646 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66666

Abstract: One illustrative method disclosed includes, among other things, forming a vertically oriented semiconductor structure above a doped well region defined in a semiconductor substrate, the semiconductor structure comprising a lower source/drain region and an upper source/drain region, wherein the lower source/drain region physically contacts the upper surface of the substrate, forming a counter-doped isolation region in the substrate, forming a metal silicide region in the substrate above the counter-doped isolation region, wherein the metal silicide region is in physical contact with the lower source/drain region, and forming a lower source/drain contact structure that is conductively coupled to the metal silicide region.

公开(公告)号：US20170077301A1

公开(公告)日：2017-03-16

申请号：US14853073

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative method disclosed herein includes, among other things, forming a liner semiconductor material within a trench, the liner material defining a transistor cavity, and forming spaced-apart source/drain placeholder structures that are at least partially positioned within the transistor cavity, the spaced-apart source/drain placeholder structures defining a gate cavity therebetween where a portion of the liner semiconductor material is exposed within the gate cavity. The method further includes forming a gate structure within the gate cavity and, after forming the gate structure, removing at least a portion of the source/drain placeholder structures to define a plurality of source/drain cavities within the transistor cavity on opposite sides of the gate structure, and forming a source/drain structure in each of the source drain cavities.

Abstract translation: 本文公开的一种说明性方法包括在沟槽内形成衬里半导体材料，衬里材料限定晶体管空腔，以及形成至少部分地位于晶体管腔内的间隔开的源极/漏极占位符结构， 间隔开的源极/漏极占位符结构，其中在其间限定了一个栅极腔，其中衬里半导体材料的一部分在栅极腔内露出。 该方法还包括在栅极腔内形成栅极结构，并且在形成栅极结构之后，去除源极/漏极占位符结构的至少一部分以在晶体管腔内的多个源极/漏极空腔内 栅极结构，并且在每个源极漏极腔中形成源极/漏极结构。

公开(公告)号：US20170077297A1

公开(公告)日：2017-03-16

申请号：US14853012

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/4236 ,  H01L29/66666

Abstract: One illustrative method disclosed herein includes, among other things, forming a trench in a semiconductor substrate, forming a liner semiconductor material above the entire interior surface of the trench, the liner semiconductor material defining a transistor cavity, forming a gate structure that is at least partially positioned within the transistor cavity, and performing at least one epitaxial deposition process to form a source region structure and a drain region structure on opposite sides of the gate structure, wherein at least a portion of each of the source region structure and the drain region structure is positioned within the transistor cavity.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成沟槽，在沟槽的整个内表面上形成衬里半导体材料，衬里半导体材料限定晶体管腔，形成至少为栅极结构 部分地位于晶体管腔内，并且执行至少一个外延沉积工艺以在栅极结构的相对侧上形成源极区结构和漏极区结构，其中源极区结构和漏极区的每一个的至少一部分 结构位于晶体管腔内。

公开(公告)号：US09166025B1

公开(公告)日：2015-10-20

申请号：US14304096

申请日：2014-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7854 ,  H01L29/78618 ,  H01L29/78696

Abstract: One illustrative method includes forming at least one layer of epi semiconductor cladding material around a fin and patterning the cladding material and the fin, thereby resulting in the patterned fin being positioned under the patterned cladding material, wherein the patterned cladding material has an upper portion and a plurality of substantially vertically oriented legs extending downward from the upper portion. The method also includes selectively removing the patterned fin relative to the patterned cladding material, forming a sacrificial gate structure all around at least a portion of the cladding material, forming an epi semiconductor source/drain region on each of the substantially vertically oriented legs, and forming a final gate structure around at least a portion of the cladding material.

Abstract translation: 一种说明性方法包括在翅片周围形成至少一层外延半导体包层材料，并对包层材料和散热片进行图案化，从而导致图案化翅片位于图案化包层材料之下，其中图案化包层材料具有上部和 从上部向下延伸的多个基本垂直定向的腿。 该方法还包括相对于图案化的包层材料选择性地去除图案化的翅片，在包层材料的至少一部分周围形成牺牲栅极结构，在每个基本垂直定向的腿上形成外延半导体源极/漏极区域，以及 围绕所述包层材料的至少一部分形成最终栅极结构。