公开(公告)号：US20180122644A1

公开(公告)日：2018-05-03

申请号：US15339497

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Min Gyu SUNG ,  Chanro PARK ,  Hoon KIM

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes. A resulting semiconductor structure formed by the method is also provided.

公开(公告)号：US20180019337A1

公开(公告)日：2018-01-18

申请号：US15683228

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7827 ,  H01L21/28088 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666

Abstract: An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers, each of the sidewall spacers having vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a temporary hard mask to pattern the SiN hard mask.

公开(公告)号：US20170309522A1

公开(公告)日：2017-10-26

申请号：US15645395

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM ,  Ruilong XIE

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

公开(公告)号：US20170271163A1

公开(公告)日：2017-09-21

申请号：US15072626

申请日：2016-03-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Ruilong XIE ,  Chanro PARK ,  Hoon KIM ,  Kwan-Yong LIM

IPC: H01L21/3065 ,  H01L29/161 ,  H01L27/11 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/161

Abstract: Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.

公开(公告)号：US20200058757A1

公开(公告)日：2020-02-20

申请号：US16105102

申请日：2018-08-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Chanro PARK ,  Julien FROUGIER ,  Kangguo CHENG ,  Andre P. LABONTE

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at least one metallization feature connecting to the source and drain regions and extending over the sidewall spacers.

公开(公告)号：US20190067115A1

公开(公告)日：2019-02-28

申请号：US15683968

申请日：2017-08-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Laertis ECONOMIKOS ,  Ruilong XIE ,  Min Gyu SUNG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L29/66

Abstract: A method of manufacturing a FinFET structure involves forming a gate cut within a sacrificial gate layer and backfilling the gate cut opening with an etch selective dielectric later. Lateral etching of the dielectric layer after removing remaining portions of the sacrificial gate can be used to increase the distance between the gate cut (isolation) structure and an adjacent fin relative to methods that do not perform a step of trimming the dielectric layer.

公开(公告)号：US20170221764A1

公开(公告)日：2017-08-03

申请号：US15014150

申请日：2016-02-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon KIM ,  Min-gyu SUNG ,  Ruilong XIE ,  Chanro PARK

IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28185 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.

公开(公告)号：US20160322260A1

公开(公告)日：2016-11-03

申请号：US14699122

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro PARK ,  Sukwon HONG ,  Hoon KIM ,  Min Gyu SUNG

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/823431 ,  H01L21/28088 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823481

Abstract: The present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a recess in the dielectric layer on each side of each fin, each recess being for a metal gate; forming sidewall spacers on each side of each recess; depositing a high-k dielectric liner in each recess and on a top surface of each of the fins; depositing a metal liner over the high-k dielectric layer; depositing a non-conformal organic layer (NCOL) over a top surface of the dielectric layer to pinch-off a top of each recess; depositing an OPL and ARC over the NCOL; etching the OPL, ARC and NCOL over a portion of the dielectric layer and recesses in a first region; and etching the portion of the recesses to remove residual NCOL present at a bottom of each recess of the portion of the recesses.

Abstract translation: 本申请涉及光学平坦化层蚀刻工艺。 实施例包括形成由电介质层分离的翅片; 在每个翅片的每一侧上的电介质层中形成凹槽，每个凹槽用于金属栅极; 在每个凹部的每一侧上形成侧壁间隔物; 在每个凹部和每个翅片的顶表面上沉积高k电介质衬垫; 在高k电介质层上沉积金属衬垫; 在所述电介质层的顶表面上沉积非共形有机层（NCOL）以夹紧每个凹部的顶部; 在NCOL上放置OPL和ARC; 在第一区域中的电介质层的一部分和凹部上蚀刻OPL，ARC和NCOL; 并且蚀刻所述凹部的所述部分以除去存在于所述凹部的所述部分的每个凹部的底部的残留NCOL。

公开(公告)号：US20150168824A1

公开(公告)日：2015-06-18

申请号：US14106219

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei SUN ,  Chanro PARK ,  Wenhui WANG ,  Hui ZANG

IPC: G03F1/62 ,  G03F1/22

CPC classification number: G03F1/142 ,  G03F1/22 ,  G03F1/62 ,  G03F1/64

Abstract: A method of forming an improved EUV mask and pellicle with airflow between the area enclosed by the mask and pellicle and the area outside the mask and pellicle and the resulting device are disclosed. Embodiments include forming a frame around a patterned area on an EUV mask; forming a membrane over the frame; and forming holes in the frame.

Abstract translation: 公开了一种在由掩模和防护薄膜组成的区域与掩模和防护薄膜之间的区域以及所得到的装置之间形成改进的EUV掩模和防护薄膜组件的方法。 实施例包括在EUV掩模上的图案化区域周围形成框架; 在框架上形成膜; 并在框架中形成孔。

公开(公告)号：US20200176325A1

公开(公告)日：2020-06-04

申请号：US16780046

申请日：2020-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Stan TSAI

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/06 ,  H01L29/45 ,  H01L27/088 ,  H01L21/321 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.