公开(公告)号：US09373691B2

公开(公告)日：2016-06-21

申请号：US13961282

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L21/04 ,  H01L29/78 ,  H01L29/16 ,  H01L21/762

CPC classification number: H01L29/66068 ,  H01L21/049 ,  H01L21/76254 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes forming a dielectric layer on a first substrate and wafer bonding the dielectric layer of the first substrate to a second substrate including SiC with a passivating layer formed on the SiC. A portion of the first substrate is removed from a side opposite the dielectric layer. The dielectric layer is patterned to form a gate dielectric for a field effect transistor formed on the second substrate.

Abstract translation: 一种形成半导体器件的方法包括在第一衬底上形成电介质层，并将第一衬底的电介质层与包含SiC的第二衬底相结合，并在SiC上形成钝化层。 从与电介质层相对的一侧去除第一衬底的一部分。 对电介质层进行构图以形成用于形成在第二衬底上的场效应晶体管的栅极电介质。

公开(公告)号：US09331229B2

公开(公告)日：2016-05-03

申请号：US14147939

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L31/00 ,  H01L21/00 ,  H01L31/075 ,  H01L31/0304 ,  H01L31/074

CPC classification number: H01L31/075 ,  H01L31/03046 ,  H01L31/074 ,  Y02E10/544 ,  Y02P70/521

Abstract: An InxGa1-xAs interlayer is provided between a III-V base and an intrinsic amorphous semiconductor layer of a heterojunction III-V solar cell structure. Improved surface passivation and open circuit voltage may be obtained through the incorporation of the interlayer within the structure.

Abstract translation: 在III-V基极和异质结III-V族太阳能电池结构的本征非晶半导体层之间提供In x Ga 1-x As夹层。 可以通过在结构内并入中间层来获得改进的表面钝化和开路电压。

公开(公告)号：US09240432B2

公开(公告)日：2016-01-19

申请号：US14020473

申请日：2013-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/146

CPC classification number: H01L27/14692 ,  H01L27/1461 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14687

Abstract: A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry.

公开(公告)号：US09231094B2

公开(公告)日：2016-01-05

申请号：US13898585

申请日：2013-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Bahman Hekmatshoartabari ,  Davood Shahrjerdi

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/283 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L29/7786 ,  H01L21/0272 ,  H01L21/283 ,  H01L21/31144 ,  H01L29/0843 ,  H01L29/207 ,  H01L29/267 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/456 ,  H01L29/475 ,  H01L29/66431 ,  H01L29/66462

Abstract: Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench. Metallization is performed on physically exposed surfaces of the elemental semiconductor material portions in the source trench and the drain trench by depositing a metal and inducing interaction with the metal and the at least one elemental semiconductor material. A metal semiconductor alloy of the metal and the at least one elemental semiconductor material can be performed at a temperature lower than 600° C. to provide a high electron mobility transistor with a well-defined device profile and reliable metallization contacts.

Abstract translation: 使用栅电极作为蚀刻掩模来凹陷顶部化合物半导体层的部分以形成源极沟槽和漏极沟槽。 采用低温外延工艺在源极沟槽和漏极沟槽中沉积包括至少一种元素半导体材料的半导体材料。 通过沉积金属并诱导与金属和至少一种元素半导体材料的相互作用，在源沟槽和漏极沟槽中的元素半导体材料部分的物理暴露的表面上进行金属化。 可以在低于600℃的温度下进行金属和至少一种元素半导体材料的金属半导体合金，以提供具有良好限定的器件轮廓和可靠的金属化接触的高电子迁移率晶体管。

公开(公告)号：US09530843B2

公开(公告)日：2016-12-27

申请号：US14738336

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Davood Shahrjerdi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/324

CPC classification number: H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/31144 ,  H01L21/324 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/78687

Abstract: A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

Abstract translation: 一种平面半导体器件，包括绝缘体上半导体（SOI）衬底，源极和漏极部分具有由多层应变通道分离的小于10nm的厚度。 SOI层的多层应变通道包括存在于SOI衬底的掩埋介电层上的第一晶格尺寸的第一层和与第一层直接接触的第二晶格尺寸的第二层 的多层应变通道部分。 功能栅极结构存在于SOI衬底的多层应变通道部分上。 具有多层通道的半导体器件也可以是finFET半导体器件。

公开(公告)号：US09240355B2

公开(公告)日：2016-01-19

申请号：US14705397

申请日：2015-05-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L21/84 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/861

Abstract: An electrical device including a first conductivity semiconductor device present in a first semiconductor device region of an SOI substrate, and a second conductivity semiconductor device present in a second semiconductor device region of the SOI substrate. The electrical device also includes a diode present within a diode region of the SOI substrate that includes a first doped layer of a first conductivity semiconductor material that is present on an SOI layer of the SOI substrate. The first doped layer includes a first plurality of protrusions extending from a first connecting base portion. The semiconductor diode further includes a second doped layer of the second conductivity semiconductor material present over the first doped layer. The second doped layer including a second plurality of protrusions extending from a second connecting base portion. The second plurality of protrusions is present between and separating the first plurality of protrusions.

Abstract translation: 一种电气装置，包括存在于SOI衬底的第一半导体器件区域中的第一导电半导体器件和存在于SOI衬底的第二半导体器件区域中的第二导电半导体器件。 电子器件还包括存在于SOI衬底的二极管区域内的二极管，其包括存在于SOI衬底的SOI层上的第一导电半导体材料的第一掺杂层。 第一掺杂层包括从第一连接基部延伸的第一多个突起。 半导体二极管还包括存在于第一掺杂层上的第二导电半导体材料的第二掺杂层。 第二掺杂层包括从第二连接基部延伸的第二多个突起。 第二多个突起存在于并分离第一多个突起之间。

公开(公告)号：US09368420B2

公开(公告)日：2016-06-14

申请号：US14732689

申请日：2015-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephen W. Bedell ,  Wilfried E. Haensch ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/01 ,  H01L23/14 ,  H01L27/12 ,  H01L27/092 ,  H01L23/538 ,  H01L21/762

CPC classification number: H01L23/14 ,  H01L21/4846 ,  H01L21/7624 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/5387 ,  H01L27/092 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

公开(公告)号：US09356114B2

公开(公告)日：2016-05-31

申请号：US14042951

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  Bahman Hekmatshoartabari ,  Tak H. Ning ,  Davood Shahrjerdi

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/283 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L21/308

CPC classification number: H01L29/66242 ,  H01L21/283 ,  H01L21/3086 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/7371

Abstract: A method of forming the heterojunction bipolar transistor that includes providing a stack of a base layer, an extrinsic base layer, a first metal containing layer, and a dielectric cap layer. The dielectric cap layer and the first metal containing layer may be etched to provide a base contact and a dielectric cap. Exposed portions of the base layer may be etched selectively to the dielectric cap. A remaining portion of the base layer provides the base region. A hydrogenated silicon containing layer may be deposited with a low temperature deposition method. At least a portion of the hydrogenated silicon containing layer is formed on at least sidewalls of the base region. A second metal containing layer may be formed on the hydrogenated silicon containing layer. The second metal containing and the hydrogenated silicon containing layer may be etched to provide an emitter region and a collector region.

Abstract translation: 一种形成异质结双极晶体管的方法，其包括提供基底层，非本征基底层，第一金属含量层和电介质盖层的叠层。 可以蚀刻电介质盖层和第一含金属层以提供基极接触和电介质盖。 基底层的暴露部分可以选择性地蚀刻到电介质盖。 基层的剩余部分提供基区。 可以用低温沉积法沉积氢化含硅层。 氢化含硅层的至少一部分形成在基底区域的至少侧壁上。 可以在含氢硅层上形成第二含金属层。 可以蚀刻包含第二金属和含氢硅的层，以提供发射极区域和集电极区域。

公开(公告)号：US09224755B2

公开(公告)日：2015-12-29

申请号：US14020098

申请日：2013-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L21/00 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L27/3262 ,  H01L21/7624 ,  H01L21/76254 ,  H01L27/1218 ,  H01L27/1262 ,  H01L27/1266 ,  H01L27/3248 ,  H01L51/5218 ,  H01L51/5221 ,  H01L51/5237 ,  H01L2227/323 ,  H01L2227/326 ,  H01L2251/5338

Abstract: High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer.

Abstract translation: 使用适用于柔性基板的技术制造高分辨率有源矩阵结构。 包括有源半导体器件的背板层使用绝缘体上半导体衬底形成。 使用层转移技术或化学/机械加工使衬底变薄。 在衬底的半导体层上形成驱动晶体管以及提供计算或感测等其它功能的附加电路。 与诸如有机发光二极管的无源器件的接触可以由形成在衬底的手柄层中的重掺杂区域提供，然后被隔离。 可以在用作沟道层的半导体层上形成栅极电介质层，或者可以将衬底的绝缘体层用作栅极介电层。