公开(公告)号：US20170373007A1

公开(公告)日：2017-12-28

申请号：US15698793

申请日：2017-09-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Keith H. Tabakman ,  Patrick D. Carpenter ,  Guillaume Bouche ,  Michael V. Aquilino

IPC: H01L23/535 ,  H01L29/417 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.

公开(公告)号：US09818876B1

公开(公告)日：2017-11-14

申请号：US15349358

申请日：2016-11-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a FinFET device includes a self-aligned contact etch where a source/drain contact module is performed prior to a replacement metal gate (RMG) module. In particular, the method involves forming a sacrificial gate over the channel region of a fin, and an interlayer dielectric over adjacent source/drain regions of the fin. An etch mask is then used to protect source/drain contact regions and enable the removal of the interlayer dielectric from outside of the protected area, e.g., between adjacent fins.

公开(公告)号：US09818641B1

公开(公告)日：2017-11-14

申请号：US15271497

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L27/11

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/11

Abstract: A method includes providing a structure having a first, second and third hardmask layer and a mandrel layer disposed respectively over a dielectric stack. An array of mandrels, a beta trench and a gamma trench are patterned into the structure. First inner spacers are formed on sidewalls of the beta trench and second inner spacers are formed on sidewalls of the gamma trench. The first and second inner spacers form a portion of a pattern. The pattern is etched into the dielectric stack to form an array of mandrel and non-mandrel metal lines extending in a Y direction and being self-aligned in an X direction. The portion of the pattern formed by the first and second inner spacers forms a first pair of cuts in a mandrel line and a second pair of cuts in a non-mandrel line respectively. The cuts are self-aligned in the Y direction.

公开(公告)号：US09818623B2

公开(公告)日：2017-11-14

申请号：US15077480

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  Guillaume Bouche ,  Byoung Youp Kim ,  Craig Michael Child, Jr.

IPC: H01L21/302 ,  H01L21/3213 ,  H01L21/32

CPC classification number: H01L21/32 ,  H01L21/0337 ,  H01L21/31144

Abstract: A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

公开(公告)号：US20170263715A1

公开(公告)日：2017-09-14

申请号：US15067540

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Sudharshanan Raghunathan ,  Andy Chi-Hung Wei ,  Jason Eugene Stephens ,  Vikrant Kumar Chauhan ,  David Michael Permana

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/49 ,  H01L21/311

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0273 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.

公开(公告)号：US09691626B1

公开(公告)日：2017-06-27

申请号：US15077384

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76816 ,  H01L23/528

Abstract: A method of forming a pattern includes providing a structure having an etch mask layer disposed over a pattern layer disposed over a dielectric layer. Disposing first and second trench plugs having different material compositions in the etch mask layer, the first and second trench plugs overlaying gamma and beta block mask portions respectively of the pattern layer. Forming an array of self-aligned spacers disposed on sidewalls of mandrels, the spacers and mandrels defining alternating beta and gamma regions extending normally to the dielectric layer, the gamma region and beta regions extending though portions of the first and second trench plug respectively. Selectively etching the structure to remove any portion of the first trench plug within the beta region and any portion of the second trench plug within the gamma region. Selectively etching the structure to form a pattern in the pattern layer including the block mask portions.

公开(公告)号：US09679805B2

公开(公告)日：2017-06-13

申请号：US15336589

申请日：2016-10-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Mark A. Zaleski

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L21/76834 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76838 ,  H01L21/76897 ,  H01L23/52 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density.

公开(公告)号：US09660075B2

公开(公告)日：2017-05-23

申请号：US15051734

申请日：2016-02-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shao Ming Koh ,  Guillaume Bouche ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L21/84 ,  H01L29/78 ,  H01L27/092 ,  H01L21/311 ,  H01L29/45 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/167 ,  H01L29/161 ,  H01L21/02 ,  H01L29/08 ,  H01L29/24 ,  H01L29/66 ,  H01L29/417 ,  H01L27/12

CPC classification number: H01L29/7839 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7848

Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.

公开(公告)号：US09640625B2

公开(公告)日：2017-05-02

申请号：US14261823

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Gabriel Padron Wells ,  Andre P. Labonte ,  Jing Wan

IPC: H01L29/76 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L29/41775 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897

Abstract: Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.

公开(公告)号：US09508642B2

公开(公告)日：2016-11-29

申请号：US14463803

申请日：2014-08-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Mark A. Zaleski

IPC: H01L21/4763 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/52 ,  H01L21/311

CPC classification number: H01L21/76834 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76838 ,  H01L21/76897 ,  H01L23/52 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density.

Abstract translation: 本发明的实施例提供了一种在线结构的后端中自对准金属切割的方法。 牺牲Mx + 1线形成在金属Mx线之上。 每个Mx + 1牺牲线上形成间隔。 使用间隔件之间的间隙来确定切割到Mx金属线的位置和厚度。 这样可确保Mx金属线切割不会侵入连接Mx和Mx + 1电平的通孔。 它还允许通过外壳规则降低限制，从而增加电路密度。