公开(公告)号：US09818651B2

公开(公告)日：2017-11-14

申请号：US15067953

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285 ,  H01L21/027 ,  H01L27/092 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L21/823871 ,  G06F17/5072 ,  H01L21/027 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09779943B2

公开(公告)日：2017-10-03

申请号：US15053818

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens

IPC: H01L21/4763 ,  H01L21/033 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/0337 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228

Abstract: A hard mask is formed into lines and bridges two adjacent lines using mandrels, spacers for the mandrels and a lithographic process for each bridge to create a metal line pattern in a layer of an interconnect structure with a line pitch below lithographic resolution.

公开(公告)号：US09576735B2

公开(公告)日：2017-02-21

申请号：US14298040

申请日：2014-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roderick Alan Augur ,  Jason Eugene Stephens

IPC: H01L49/02 ,  H01L23/522 ,  H01G4/30 ,  H01G4/005 ,  H01G4/06 ,  H01G4/38 ,  H01G4/01 ,  H01G4/232

CPC classification number: H01G4/30 ,  H01G4/005 ,  H01G4/01 ,  H01G4/06 ,  H01G4/232 ,  H01G4/385 ,  H01L23/5223 ,  H01L28/88 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor structure includes a first metal layer including a first plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a second metal layer including a second plurality of horizontally-spaced neutral conductive lines positioned horizontally between a second plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a third metal layer positioned vertically below the first metal layer and above the second metal layer, the third metal layer including a third plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced low voltage conductive lines. The first plurality of low voltage lines are positioned vertically between the first and second plurality of neutral lines.

Abstract translation: 电容器结构包括第一金属层，第一金属层包括在第一多个水平间隔的高压导电线之间水平定位的第一多个水平间隔的中性导电线。 电容器结构还包括第二金属层，第二金属层包括位于第二多个水平间隔的高压导电线之间水平定位的第二多个水平间隔的中性导电线。 所述电容器结构还包括位于所述第一金属层的垂直下方且位于所述第二金属层的上方的第三金属层，所述第三金属层包括第三多个水平间隔的中性导电线，其水平位于第一多个水平间隔的低电压 导线。 第一组多个低压线路垂直地定位在第一和第二多个中性线之间。

公开(公告)号：US10559503B2

公开(公告)日：2020-02-11

申请号：US15728445

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/027 ,  H01L27/092 ,  G06F17/50 ,  H01L21/768 ,  H01L27/088

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US10262941B2

公开(公告)日：2019-04-16

申请号：US15136384

申请日：2016-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens ,  Tuhin Guha Neogi ,  Kai Sun ,  Deniz Elizabeth Civay ,  David Charles Pritchard ,  Andy Wei

IPC: H01L21/33 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09818640B1

公开(公告)日：2017-11-14

申请号：US15271475

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  Guillaume Bouche

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L23/528

Abstract: A method includes providing a structure having a first hardmask layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer. A gamma trench is patterned into the second hardmask layer and between the mandrels. Self-aligned inner spacers are formed on sidewalls of the gamma trench, the inner spacers forming a portion of a pattern. The pattern is etched into the dielectric stack to form an array of alternating mandrel and non-mandrel metal lines extending in a Y direction and being self-aligned in a perpendicular X direction. The portion of the pattern formed by the inner spacers is utilized to form a pair of non-mandrel line cuts in a non-mandrel line. The non-mandrel line cuts are self-aligned in the Y direction.

公开(公告)号：US09812396B1

公开(公告)日：2017-11-07

申请号：US15175495

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  Guillaume Bouche ,  Shreesh Narasimha ,  Patrick Ryan Justison ,  Byoung Youp Kim ,  Craig Michael Child, Jr.

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L23/5286 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283

Abstract: A method includes providing a starting interconnect structure for semiconductor device(s), the starting interconnect structure including a first metallization layer with a first power rail. The method further includes forming a second metallization layer over the first metallization layer with a second power rail, and directly electrically connecting the first power rail and the second power rail, the directly electrically connecting including forming metal-filled vias between the first power rail and the second power rail. The method further includes forming additional metallization layer(s) over the second metallization layer with additional power rail(s), and directly electrically connecting each of the additional power rail(s) to a power rail of a metallization layer directly below.

公开(公告)号：US09530689B2

公开(公告)日：2016-12-27

申请号：US14684949

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Deniz Elizabeth Civay ,  Jason Eugene Stephens ,  Jiong Li ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76811 ,  H01L21/76816

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract translation: 提供了制造集成电路的方法。 一种方法包括分解用于半导体器件层的主图案布局，该半导体器件层包括目标金属线，目标金属线与目标互连通孔/触点成为第一子图案和第二子图案。 目标金属线被分解为作为第一子图案的一部分的第一线特征图案和作为第二子图案的一部分的第二线特征图案，使得第一和第二线特征图案具有限定 对应于目标互连通孔/触点的针脚。 生成对应于第一子图案的第一光掩模。 生成对应于第二子图案的第二光掩模。

公开(公告)号：US09436081B2

公开(公告)日：2016-09-06

申请号：US14205569

申请日：2014-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  David Pritchard

IPC: G03F1/72

CPC classification number: G03F1/72

Abstract: A method is provided, in which a masking reticle including a plurality of pattern blocks is modified, the modifying including: identifying a first pattern block and a second pattern block of the plurality of pattern blocks where at least a first portion of the first pattern block and a second portion of the second pattern block are in parallel relation; and reducing a length of the first portion of the first pattern block when a transverse separation S between corresponding length edges of the first portion of the first pattern block the second portion of the second pattern block falls within a pre-defined forbidden pitch range for the masking reticle. The method may include repeating the identifying and reducing of pairs of pattern blocks on the mask reticle to remove portions of pattern block pairs spaced apart by a transverse separation falling within a forbidden-pitch range.

Abstract translation: 提供了一种方法，其中修改包括多个图案块的掩蔽掩模版，所述修改包括：识别所述多​​个图案块中的第一图案块和第二图案块，其中所述第一图案块的至少第一部分 并且所述第二图案块的第二部分是平行关系的; 以及当第一图案块的第一部分的相应长度边缘之间的横向间隔S与第二图案块的第二部分之间的横向间隔S落入预定义的禁止间距范围内时，减小第一图案块的第一部分的长度， 掩蔽掩模版。 该方法可以包括重复识别和减少掩模掩模版上的图案块对以去除通过落在禁止间距范围内的横向间隔间隔的图案块对的部分。

公开(公告)号：US10181420B2

公开(公告)日：2019-01-15

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  David Michael Permana ,  Guillaume Bouche ,  Andy Wei ,  Mark Zaleski ,  Anbu Selvam K M Mahalingam ,  Craig Michael Child, Jr. ,  Roderick Alan Augur ,  Shyam Pal ,  Linus Jang ,  Xiang Hu ,  Akshey Sehgal

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.