公开(公告)号：US09806221B2

公开(公告)日：2017-10-31

申请号：US15441345

申请日：2017-02-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  John J. Ellis-Monaghan ,  Marwan H. Khater ,  Jason S. Orcutt

IPC: H01L31/105 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/0392 ,  H01L31/0312 ,  H01L31/0352 ,  H01L31/103

CPC classification number: H01L31/1812 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/035272 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/1037 ,  H01L31/109 ,  H01L31/1864 ,  H01L31/1872 ,  Y02E10/50

Abstract: Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.

公开(公告)号：US09653566B2

公开(公告)日：2017-05-16

申请号：US14958345

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES Inc

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater ,  Anthony K. Stamper

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/66242 ,  H01L29/0649 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.

公开(公告)号：US20170062647A1

公开(公告)日：2017-03-02

申请号：US15227081

申请日：2016-08-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  John C. S. Hall ,  Marwan H. Khater ,  Edward W. Kiewra ,  Steven M. Shank

IPC: H01L31/18 ,  H01L31/0203 ,  H01L31/028 ,  H01L31/0216 ,  H01L27/144 ,  H01L31/105

CPC classification number: H01L31/1808 ,  H01L27/1443 ,  H01L27/1446 ,  H01L27/14629 ,  H01L31/0203 ,  H01L31/02161 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/103 ,  H01L31/105 ,  H01L31/1872

Abstract: Disclosed are a method of forming a photodetector and a photodetector structure. In the method, a polycrystalline or amorphous light-absorbing layer is formed on a dielectric layer such that it is in contact with a monocrystalline semiconductor core of an optical waveguide. The light-absorbing layer is then encapsulated in one or more strain-relief layers and a rapid melting growth (RMG) process is performed to crystallize the light-absorbing layer. The strain-relief layer(s) are tuned for controlled strain relief so that, during the RMG process, the light-absorbing layer remains crack-free. The strain-relief layer(s) are then removed and an encapsulation layer is formed over the light-absorbing layer (e.g., filling in surface pits that developed during the RMG process). Subsequently, dopants are implanted through the encapsulation layer to form diffusion regions for PIN diode(s). Since the encapsulation layer is relatively thin, desired dopant profiles can be achieved within the diffusion regions.

Abstract translation: 公开了一种形成光电检测器和光电检测器结构的方法。 在该方法中，在电介质层上形成多晶或非晶光吸收层，使其与光波导的单晶半导体芯接触。 然后将光吸收层封装在一个或多个应变消除层中，并进行快速熔融生长（RMG）工艺以使光吸收层结晶。 调节应变消除层以控制应变消除，使得在RMG过程期间，光吸收层保持无裂纹。 然后去除应变消除层，并且在光吸收层上形成封装层（例如，填充在RMG工艺期间产生的表面凹坑中）。 随后，通过封装层注入掺杂剂以形成用于PIN二极管的扩散区域。 由于封装层相对较薄，所以可以在扩散区域内实现所需的掺杂分布。

公开(公告)号：US20170054049A1

公开(公告)日：2017-02-23

申请号：US14830870

申请日：2015-08-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  John J. Ellis-Monaghan ,  Marwan H. Khater ,  Jason S. Orcutt

IPC: H01L31/109 ,  H01L31/0352 ,  H01L31/18 ,  H01L31/028

CPC classification number: H01L31/1812 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/035272 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/1037 ,  H01L31/109 ,  H01L31/1864 ,  H01L31/1872 ,  Y02E10/50

Abstract: Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.

Abstract translation: 各种具体实施方案包括形成光电检测器的方法，包括：形成包括设置在掺杂硅（Si）层和锗层（Ge）之间的阻挡层的结构，所述阻挡层包括结晶窗口; 并且退火该结构以通过晶化窗口将Ge转化为硅锗（SiGe）的第一组成和掺杂Si至SiGe的第二组成。

公开(公告)号：US09245951B1

公开(公告)日：2016-01-26

申请号：US14487582

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/0826 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7325 ,  H01L29/7378

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.

Abstract translation: 双极结型晶体管的器件结构和制造方法。 在衬底的顶表面上形成一层。 在该层中形成沟槽并且具有多个侧壁，其宽度在相对的一对侧壁之间的宽度随着距离衬底顶表面的距离的增加而变化。 在沟槽中形成双极结型晶体管的集电极基座。

公开(公告)号：US09722057B2

公开(公告)日：2017-08-01

申请号：US14747668

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Marwan H. Khater

IPC: H01L29/737 ,  H01L21/265 ,  H01L21/762 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L21/26586 ,  H01L21/76237 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732

Abstract: Device structure and fabrication methods for a bipolar junction transistor. A trench isolation region is formed that bounds an active device region along a sidewall. A dielectric region is formed that extends laterally from the sidewall of the active device region into the active device region. The dielectric region is located beneath a top surface of the active device region such that a section of the active device region is located between the top surface and the dielectric region.

公开(公告)号：US09647165B2

公开(公告)日：2017-05-09

申请号：US14830870

申请日：2015-08-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  John J. Ellis-Monaghan ,  Marwan H. Khater ,  Jason S. Orcutt

IPC: H01L31/105 ,  H01L31/0232 ,  H01L31/109 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/18

CPC classification number: H01L31/1812 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/035272 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/1037 ,  H01L31/109 ,  H01L31/1864 ,  H01L31/1872 ,  Y02E10/50

Abstract: Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.

公开(公告)号：US09466753B1

公开(公告)日：2016-10-11

申请号：US14837812

申请日：2015-08-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  John C. S. Hall ,  Marwan H. Khater ,  Edward W. Kiewra ,  Steven M. Shank

IPC: H01L31/18 ,  H01L31/103 ,  H01L31/0203 ,  H01L31/028 ,  H01L27/144

CPC classification number: H01L31/1808 ,  H01L27/1443 ,  H01L27/1446 ,  H01L27/14629 ,  H01L31/0203 ,  H01L31/02161 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/103 ,  H01L31/105 ,  H01L31/1872

Abstract: Disclosed are a method of forming a photodetector and a photodetector structure. In the method, a polycrystalline or amorphous light-absorbing layer is formed on a dielectric layer such that it is in contact with a monocrystalline semiconductor core of an optical waveguide. The light-absorbing layer is then encapsulated in one or more strain-relief layers and a rapid melting growth (RMG) process is performed to crystallize the light-absorbing layer. The strain-relief layer(s) are tuned for controlled strain relief so that, during the RMG process, the light-absorbing layer remains crack-free. The strain-relief layer(s) are then removed and an encapsulation layer is formed over the light-absorbing layer (e.g., filling in surface pits that developed during the RMG process). Subsequently, dopants are implanted through the encapsulation layer to form diffusion regions for PIN diode(s). Since the encapsulation layer is relatively thin, desired dopant profiles can be achieved within the diffusion regions.

Abstract translation: 公开了一种形成光电检测器和光电检测器结构的方法。 在该方法中，在电介质层上形成多晶或非晶光吸收层，使其与光波导的单晶半导体芯接触。 然后将光吸收层封装在一个或多个应变消除层中，并进行快速熔融生长（RMG）工艺以使光吸收层结晶。 调节应变消除层以控制应变消除，使得在RMG过程期间，光吸收层保持无裂纹。 然后去除应变消除层，并且在光吸收层上形成封装层（例如，填充在RMG工艺期间产生的表面凹坑中）。 随后，通过封装层注入掺杂剂以形成用于PIN二极管的扩散区域。 由于封装层相对较薄，所以可以在扩散区域内实现所需的掺杂分布。

公开(公告)号：US09318551B2

公开(公告)日：2016-04-19

申请号：US14527042

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Marwan H. Khater

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/732 ,  H01L29/735 ,  H01L29/737 ,  H01L21/76

CPC classification number: H01L29/0653 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7325 ,  H01L29/735 ,  H01L29/737

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region.

公开(公告)号：US09236287B2

公开(公告)日：2016-01-12

申请号：US13667389

申请日：2012-11-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Solomon Assefa ,  William M. Green ,  Marwan H. Khater ,  Yurii A. Vlasov

IPC: H01L21/762

CPC classification number: H01L21/76205 ,  H01L21/0274 ,  H01L21/76232 ,  H01L21/76281 ,  H01L21/76283

Abstract: Photonic SOI devices are formed by lateral epitaxy of a deposited non-crystalline semiconductor layer over a localized buried oxide created by a trench isolation process or by thermal oxidation. Specifically, and after forming a trench into a semiconductor substrate, the trench can be filled with an oxide by a deposition process or a thermal oxidation can be performed to form a localized buried oxide within the semiconductor substrate. In some embodiments, the oxide can be recessed to expose sidewall surfaces of the semiconductor substrate. Next, a non-crystalline semiconductor layer is formed and then a solid state crystallization is preformed which forms a localized semiconductor-on-insulator layer. During the solid state crystallization process portions of the non-crystalline semiconductor layer that are adjacent exposed sidewall surfaces of the substrate are crystallized.

Abstract translation: 通过在通过沟槽隔离工艺或通过热氧化产生的局部掩埋氧化物上沉积的非晶体半导体层的横向外延形成光子学SOI器件。 具体地说，并且在将半导体衬底形成沟槽之后，可以通过沉积工艺填充沟槽，或者可以进行热氧化以在半导体衬底内形成局部掩埋氧化物。 在一些实施例中，氧化物可以凹入以暴露半导体衬底的侧壁表面。 接下来，形成非晶半导体层，然后进行形成局部绝缘体上半导体层的固态结晶。 在固态结晶处理期间，非晶半导体层的与衬底的暴露的侧壁表面相邻的部分结晶。