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    Methods of forming transistor structures including forming channel material after formation processes to prevent damage to the channel material
    15.
    发明授权
    Methods of forming transistor structures including forming channel material after formation processes to prevent damage to the channel material 有权
    形成晶体管结构的方法，包括在形成工艺之后形成沟道材料以防止损坏沟道材料

    公开(公告)号：US09570588B2

    公开(公告)日：2017-02-14

    申请号：US14883045

    申请日：2015-10-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat Kerem Akarvardar ,  Steven Bentley

    IPC: H01L29/66 ,  H01L21/306 ,  H01L21/3213

    CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/32134 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/785

    Abstract: Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure.

    Abstract translation: 提供了制造晶体管结构的方法，所述方法包括：形成具有上翅片部分和下翅片部分的翅片结构，所述上翅片部分包括牺牲材料; 在翅片上形成栅极结构; 选择性地去除所述上翅片部分以在所述门结构和所述下翅片部分之间形成隧道; 以及在隧道中提供通道材料以限定栅极结构的沟道区域。 牺牲材料可以是可以选择性地蚀刻而不蚀刻下部翅片部分的材料的材料。 可以进一步提供沟道材料以形成晶体管结构的源极和漏极区域，这可能导致无连接的FinFET结构。

    Methods of forming strained channel regions on FinFET devices
    16.
    发明授权
    Methods of forming strained channel regions on FinFET devices 有权
    在FinFET器件上形成应变沟道区的方法

    公开(公告)号：US09502507B1

    公开(公告)日：2016-11-22

    申请号：US15012107

    申请日：2016-02-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser

    IPC: H01L21/283 ,  H01L21/306 ,  H01L29/10 ,  H01L29/66 ,  H01L29/165 ,  H01L29/16

    CPC classification number: H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    Abstract: One illustrative method disclosed herein includes, among other things, removing at least a portion of a vertical height of portions of an overall fin structure that are not covered by a gate structure so as to result in the definition of a fin cavity in a layer of insulating material and the definition of a remaining portion of the overall fin structure that is positioned under the gate structure, wherein the remaining portion comprises a channel portion and a lower portion located under the channel portion. The method continues with the formation of a first semiconductor material within at least the fin cavity and the formation of a second semiconductor material on the first semiconductor material and on exposed edges of the channel portion.

    Abstract translation: 本文公开的一种说明性方法包括除去未被栅极结构覆盖的整个鳍结构的部分的垂直高度的至少一部分，以便导致在一层中的翅片腔的定义 绝缘材料和定位在栅极结构下方的整个鳍结构的剩余部分的定义，其中剩余部分包括通道部分和位于通道部分下方的下部分。 该方法继续在至少翅片腔内形成第一半导体材料，并在第一半导体材料上形成第二半导体材料并在通道部分的暴露边缘上形成第二半导体材料。

    METHODS OF MODULATING STRAIN IN PFET AND NFET FINFET SEMICONDUCTOR DEVICES
    17.
    发明申请
    METHODS OF MODULATING STRAIN IN PFET AND NFET FINFET SEMICONDUCTOR DEVICES 有权
    在PFET和NFET FinFET半导体器件中调制应变的方法

    公开(公告)号：US20160254195A1

    公开(公告)日：2016-09-01

    申请号：US14633353

    申请日：2015-02-27

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Bruce Doris ,  Ali Khakifirooz

    IPC: H01L21/8238 ,  H01L21/762 ,  H01L29/161 ,  H01L29/16 ,  H01L21/306 ,  H01L29/78

    CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/165

    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same initial strain above a substrate, performing at least one etching process so as to cut a first fin to a first axial length and to cut a second fin to a second axial length that is less than the first axial length, wherein the cut first fin retains a first amount of the initial strain and the cut second fin retains about zero of the initial strain or a second amount of the initial strain that is less than the first amount, and forming gate structures around the first and second cut fins to form FinFET devices.

    Abstract translation: 本文公开的一种说明性方法包括形成多个初始翅片，其具有与基底相同的初始轴向长度和相同的初始应变，执行至少一个蚀刻工艺以将第一翅片切割成第一轴向 并且将第二翅片切割成小于第一轴向长度的第二轴向长度，其中切割的第一翅片保持初始应变的第一量，并且切割的第二翅片保持初始应变的约零或第二量 的初始应变小于第一量，并且围绕第一和第二切割翅片形成栅极结构以形成FinFET器件。

    Methods of forming replacement gate structures on FinFET devices and the resulting devices
    18.
    发明授权
    Methods of forming replacement gate structures on FinFET devices and the resulting devices 有权
    在FinFET器件和所产生的器件上形成替代栅极结构的方法

    公开(公告)号：US09412839B2

    公开(公告)日：2016-08-09

    申请号：US14535942

    申请日：2014-11-07

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat Kerem Akarvardar

    IPC: H01L29/66 ,  H01L29/40 ,  H01L21/311 ,  H01L21/02

    CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02362 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/311 ,  H01L29/401 ,  H01L29/66553 ,  H01L29/66795

    Abstract: One illustrative method disclosed herein includes, among other things, forming at least one layer of insulating material with a substantially planar upper surface that is positioned above the upper surface of the fin, forming a layer of sacrificial gate material on the layer of insulating material, the layer of sacrificial gate material having an as-deposited upper surface and a substantially uniform thickness, forming a layer of gate cap material on the as-deposited upper surface of the layer of sacrificial gate material, forming a patterned sacrificial gate structure comprised of at least the gate cap material and the sacrificial gate material, forming a sidewall spacer adjacent the patterned sacrificial gate structure, removing the patterned sacrificial gate structure and replacing it with a replacement gate structure.

    Abstract translation: 本文公开的一种说明性方法包括形成至少一层具有基本平坦的上表面的绝缘材料层，所述绝缘材料层位于鳍的上表面之上，在绝缘材料层上形成牺牲栅极材料层， 牺牲栅极材料层具有沉积的上表面和基本上均匀的厚度，在牺牲栅极材料层的沉积的上表面上形成栅极盖材料层，形成图案化的牺牲栅极结构，其包括在 至少栅极盖材料和牺牲栅极材料，形成邻近图案化的牺牲栅极结构的侧壁间隔物，去除图案化的牺牲栅极结构并用替代栅极结构代替。

    METHODS OF FORMING FIN ISOLATION REGIONS UNDER TENSILE-STRAINED FINS ON FINFET SEMICONDUCTOR DEVICES
    19.
    发明申请
    METHODS OF FORMING FIN ISOLATION REGIONS UNDER TENSILE-STRAINED FINS ON FINFET SEMICONDUCTOR DEVICES 有权
    在FINFET半导体器件上形成紧固态FINS下的熔融分离区域的方法

    公开(公告)号：US20160225676A1

    公开(公告)日：2016-08-04

    申请号：US14608815

    申请日：2015-01-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser

    IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/762 ,  H01L29/165 ,  H01L21/02

    CPC classification number: H01L21/845 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/165

    Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.

    Abstract translation: 本文公开的一种说明性方法包括形成复合翅片结构，该复合翅片结构由具有第一锗浓度的第一含锗半导体材料和位于第一锗浓度的拉伸应变第二半导体材料（具有较小的锗浓度）组成 第一含锗半导体材料，并且进行热退火工艺以将复合翅片结构的第一含锗半导体材料部分转换成位于第二半导体材料下方的含锗氧化物隔离区域，该第一半导体材料是拉伸应变末端鳍 用于NMOS FinFET器件。

    FinFET device including a uniform silicon alloy fin
    20.
    发明授权
    FinFET device including a uniform silicon alloy fin 有权
    FinFET器件包括均匀的硅合金翅片

    公开(公告)号：US09406803B2

    公开(公告)日：2016-08-02

    申请号：US14676239

    申请日：2015-04-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  Steven Bentley

    IPC: H01L21/326 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L21/02 ,  H01L21/324

    CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/161

    Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

    Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在所述散热片和所述基板的暴露的表面部分上形成硅合金材料。 执行热处理以从硅合金材料和翅片限定硅合金翅片，并且从硅合金材料和基底的暴露表面部分限定硅合金表面部分。 半导体器件包括衬底，限定在衬底上的鳍，鳍包括硅合金并且具有基本上垂直的侧壁，以及衬底上的与硅相邻的硅合金表面部分。

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