公开(公告)号：US09177871B2

公开(公告)日：2015-11-03

申请号：US14143362

申请日：2013-12-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Peter Baars ,  Bastian Haussdoerfer

IPC: H01L21/8238 ,  H01L21/285 ,  H01L21/265 ,  H01L21/311

CPC classification number: H01L21/823864 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7848

Abstract: An issue arises when manufacturing semiconductor circuits including PFETs with an SiGe alloy embedded in their source/drain regions and NFETs without any embedded SiGe alloy. In this case, the thickness of the NFET spacers is considerably greater than that of the PFET spacers. In order to alleviate this asymmetry in spacer thickness, a manufacturing flow is proposed wherein a spacer-reducing etching process is introduced before the salicidation. The etching process is performed directly after the ion implantation performed in order to form deep regions of source/drain regions of the NFETs. Thus, the spacer-reducing etching process may be performed in the presence of the same mask used during the NFET deep implantations. The spacer-reducing etching process results in thinning of the NFET spacer structures, thus alleviating the spacer thickness imbalance between NFETs and PFETs.

Abstract translation: 当制造半导体电路时，包括在其源极/漏极区域中嵌入SiGe合金的PFET和没有任何嵌入的SiGe合金的NFET的半导体电路。 在这种情况下，NFET间隔物的厚度明显大于PFET间隔物的厚度。 为了减轻间隔物厚度的这种不对称性，提出了在盐水化之前引入间隔物减少蚀刻工艺的制造流程。 在进行离子注入之后，直接进行蚀刻处理，以形成NFET的源/漏区的深区域。 因此，间隔物减少蚀刻工艺可以在NFET深度注入期间使用的相同掩模的存在下进行。 间隔物减少蚀刻工艺导致NFET间隔物结构的变薄，从而减轻NFET和PFET之间的间隔物厚度不平衡。

公开(公告)号：US09123568B2

公开(公告)日：2015-09-01

申请号：US14086563

申请日：2013-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Richard Carter ,  Andy Wei

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L23/485 ,  H01L23/28

CPC classification number: H01L27/092 ,  H01L21/28512 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/28 ,  H01L23/485 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7847 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of NMOS transistor elements, each including a first gate electrode structure above a first active region, at least two of the plurality of first gate electrode structures including a first encapsulating stack having a first dielectric cap layer and a first sidewall spacer stack. The semiconductor device also includes a plurality of PMOS transistor elements, each including a second gate electrode structure above a second active region, wherein at least two of the plurality of second gate electrode structures include a second encapsulating stack having a second dielectric cap layer and a second sidewall spacer stack. Additionally, the first and second sidewall spacer stacks each include at least three dielectric material layers, wherein each of the three dielectric material layers of the first and second sidewall spacer stacks include the same dielectric material.

Abstract translation: 半导体器件包括多个NMOS晶体管元件，每个NMOS晶体管元件均包括在第一有源区上方的第一栅极电极结构，多个第一栅电极结构中的至少两个包括第一封装堆叠，第一封装堆叠具有第一电介质盖层和第一侧壁 间隔堆叠 半导体器件还包括多个PMOS晶体管元件，每个PMOS晶体管元件包括在第二有源区上方的第二栅极电极结构，其中多个第二栅电极结构中的至少两个包括具有第二电介质盖层和 第二侧壁间隔堆叠。 另外，第一和第二侧壁间隔堆叠每个包括至少三个介电材料层，其中第一和第二侧壁间隔物叠层的三个介电材料层中的每一个包括相同的电介质材料。

公开(公告)号：US20140319617A1

公开(公告)日：2014-10-30

申请号：US14326623

申请日：2014-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/092 ,  H01L21/76889 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/4232 ,  H01L29/4975 ,  H01L29/78

Abstract: An integrated circuit device includes a PMOS transistor and an NMOS transistor. The PMO transistor includes a gate electrode, at least one source/drain region, a first sidewall spacer positioned adjacent the gate electrode of the PMOS transistor, and a multi-part second sidewall spacer positioned adjacent the first sidewall spacer of the PMOS transistor, wherein the multi-part second sidewall spacer includes an upper spacer and a lower spacer. The NMOS transistor includes a gate electrode, at least one source/drain region, a first sidewall spacer positioned adjacent the gate electrode of the NMOS transistor, and a single second sidewall spacer positioned adjacent the first sidewall spacer of the NMOS transistor. A metal silicide region is positioned on each of the gate electrodes and on each of the at least one source/drain regions of the PMOS and the NMOS transistors.

Abstract translation: 集成电路器件包括PMOS晶体管和NMOS晶体管。 PMO晶体管包括栅极电极，至少一个源极/漏极区域，邻近PMOS晶体管的栅电极定位的第一侧壁间隔物和邻近PMOS晶体管的第一侧壁间隔物定位的多部分第二侧壁间隔物，其中 多部分第二侧壁间隔件包括上间隔件和下间隔件。 NMOS晶体管包括栅极电极，至少一个源极/漏极区域，邻近NMOS晶体管的栅电极定位的第一侧壁间隔件和邻近NMOS晶体管的第一侧壁间隔物定位的单个第二侧壁间隔物。 金属硅化物区域位于PMOS和NMOS晶体管的每个栅极电极和至少一个源极/漏极区域中的每一个上。

公开(公告)号：US20130307112A1

公开(公告)日：2013-11-21

申请号：US13947793

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Thilo Scheiper

IPC: H01L29/861

CPC classification number: H01L29/8611 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/822 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1207 ,  H01L27/127 ,  H01L29/66136

Abstract: A substrate diode device having an anode and a cathode includes a doped well positioned in a bulk layer of an SOI substrate. A first doped region is positioned in the doped well, the first doped region being for one of the anode or the cathode, the first doped region having a first long axis and a second doped region positioned in the doped well. The second doped region is separate from the first doped region, the second doped region being for the other of the anode or the cathode, the second doped region having a second long axis that is oriented at an orientation angle with respect to the first long axis.

Abstract translation: 具有阳极和阴极的衬底二极管器件包括位于SOI衬底的体层中的掺杂阱。 第一掺杂区域位于掺杂阱中，第一掺杂区域用于阳极或阴极中的一个，第一掺杂区域具有位于掺杂阱中的第一长轴和第二掺杂区。 第二掺杂区域与第一掺杂区域分开，第二掺杂区域用于阳极或阴极中的另一个，第二掺杂区域具有第二长轴，其以相对于第一长轴线的取向角定向 。

公开(公告)号：US20130154018A1

公开(公告)日：2013-06-20

申请号：US13769446

申请日：2013-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas Werner ,  Peter Baars ,  Frank Feustel

IPC: H01L23/538 ,  H01L27/088

CPC classification number: H01L23/5384 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.

Abstract translation: 本文公开了一种说明性的半导体器件，其包括具有漏极和源极区域以及栅电极结构的晶体管。 所公开的半导体器件还包括形成在第一电介质材料中的接触杆，所述接触杆连接到漏极和源极区域之一并且包括第一导电材料，所述接触棒沿晶体管的宽度方向延伸。 此外，说明性器件还包括形成在第二电介质材料中的导电线，该导电线包括具有沿晶体管的长度方向延伸的顶部宽度的上部，以及具有底部宽度延伸的下部 沿着所述长度方向小于所述上部的顶部宽度，其中所述导电线连接到所述接触杆并包括与所述第一导电材料不同的第二导电材料。

公开(公告)号：US20200251576A1

公开(公告)日：2020-08-06

申请号：US16854552

申请日：2020-04-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Elliot John Smith

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/762 ,  H01L21/306 ,  H01L27/12 ,  H01L29/786 ,  H01L21/285 ,  H01L29/423 ,  H01L29/49

Abstract: A device including an SOI substrate and an isolation structure positioned at least partially in a trench that extends through a buried insulation layer and into a semiconductor bulk substrate of the SOI substrate is disclosed. The isolation structure includes a first dielectric layer positioned in a lower portion of the trench, a first material layer positioned above the first dielectric layer, the first material layer having a material different from a material of the first dielectric layer, and a second dielectric layer positioned above the first material layer, the second dielectric layer having a material different from the material of the first material layer.

公开(公告)号：US20180240796A1

公开(公告)日：2018-08-23

申请号：US15890452

申请日：2018-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Frank Jakubowski

IPC: H01L27/06 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/84 ,  H01L21/762 ,  H01L49/02 ,  H01L29/49 ,  H01L23/31 ,  H01L29/417 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/76283 ,  H01L21/84 ,  H01L23/3178 ,  H01L23/535 ,  H01L27/108 ,  H01L27/1203 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/4916 ,  H01L29/495

Abstract: A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a second device region of a semiconductor device while covering a first device region of the semiconductor device. An insulating material is formed on sidewalls and on a bottom face of each of the plurality of openings, and a first capacitor electrode is formed in each of the plurality of openings in the presence of the insulating material, wherein each of the first capacitor electrodes includes a conductive material and partially fills a respective one of the plurality of openings.

公开(公告)号：US09793294B1

公开(公告)日：2017-10-17

申请号：US15455588

申请日：2017-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/417 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0642 ,  H01L29/16 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78684

Abstract: A semiconductor device includes an SOI substrate and a transistor device positioned in and above the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulation layer above the semiconductor bulk substrate, and a semiconductor layer above the buried insulation layer. The transistor device includes a gate structure having a gate electrode and a first cap layer covering upper and sidewall surfaces of the gate electrode. An oxide liner covers sidewalls of the gate structure and a second cap layer covers the oxide liner. A recess is located adjacent to the gate structure and is at least partially defined by an upper surface of the semiconductor layer, a bottom surface of the second cap layer and at least part of the oxide liner. Raised source/drain regions are positioned above the semiconductor layer and portions of the raised source/drain regions are positioned in the recess.

公开(公告)号：US09673210B1

公开(公告)日：2017-06-06

申请号：US15053365

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Joerg Schmid

IPC: H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L21/823842 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/165 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66833 ,  H01L29/7848 ,  H01L29/792

Abstract: A semiconductor structure including a nonvolatile memory cell element including an active region formed in a semiconductor material, a select gate structure, a dummy control gate structure and a transfer gate structure is provided. Additionally, an electrically insulating structure extending around each of the select gate structure, the dummy control gate structure and the transfer gate structure is provided. The dummy control gate structure is removed, wherein a first recess is formed in the semiconductor structure. After removing the dummy gate structure, a charge trapping layer and a layer of a control gate electrode material are deposited over the semiconductor structure. Portions of the charge trapping layer and the layer of the control gate electrode material over the electrically insulating structure are removed. Portions of the charge trapping layer and the layer of control gate electrode material in the recess provide a control gate structure of the nonvolatile memory cell.

公开(公告)号：US09634017B1

公开(公告)日：2017-04-25

申请号：US14959382

申请日：2015-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Juergen Thees

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/40 ,  H01L27/11 ,  H01L29/51 ,  H01L21/28 ,  H01L21/265 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/788 ,  H01L27/11526 ,  G11C14/00 ,  G11C16/24 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L27/11521 ,  G11C14/0063 ,  G11C16/24 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/26513 ,  H01L21/28273 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76224 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/7883

Abstract: A semiconductor structure includes a nonvolatile memory cell including a first nonvolatile bit storage element and a second nonvolatile bit storage element which have a common source region provided in a semiconductor material and a common control gate structure. Each nonvolatile bit storage element includes a drain region, a channel region, a select gate structure, a floating gate structure and an erase gate structure. The channel region has a select gate side portion and a floating gate side portion. The select gate structure is provided at the select gate side portion of the channel region and the floating gate structure is provided at the floating gate side portion of the channel region. The erase gate structure is provided above the select gate structure and adjacent the floating gate structure. The control gate structure extends above the floating gate structures of the first and second nonvolatile bit storage elements.