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    STRUCTURE WITH COUNTER DOPING REGION BETWEEN N AND P WELLS UNDER GATE STRUCTURE
    12.
    发明申请
    STRUCTURE WITH COUNTER DOPING REGION BETWEEN N AND P WELLS UNDER GATE STRUCTURE 有权

    公开(公告)号：US20210043766A1

    公开(公告)日：2021-02-11

    申请号：US16533835

    申请日：2019-08-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Baofu Zhu ,  Shesh Mani Pandey ,  Jiehui Shu ,  Sipeng Gu ,  Haiting Wang

    IPC: H01L29/78 ,  H01L29/66

    Abstract: A laterally diffused metal-oxide semiconductor (LDMOS) device is disclosed. The LDMOS FET includes a gate structure between a source region and a drain region over a p-type semiconductor substrate; and a trench isolation partially under the gate structure and between the gate structure and the drain region. A p-well is under and adjacent the source region; and an n-well is under and adjacent the drain region. A counter doping region abuts and is between the p-well and the n-well, and is directly underneath the gate structure. The counter doping region increases drain-source breakdown voltage compares to conventional approaches.

    Method of forming gate structure with undercut region and resulting device
    14.
    发明授权
    Method of forming gate structure with undercut region and resulting device 有权

    公开(公告)号：US10727133B2

    公开(公告)日：2020-07-28

    申请号：US16134708

    申请日：2018-09-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Qun Gao ,  Balaji Kannan ,  Shesh Mani Pandey ,  Haiting Wang

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

    Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.

    USING SOURCE/DRAIN CONTACT CAP DURING GATE CUT
    15.
    发明申请
    USING SOURCE/DRAIN CONTACT CAP DURING GATE CUT 审中-公开

    公开(公告)号：US20200020687A1

    公开(公告)日：2020-01-16

    申请号：US16032108

    申请日：2018-07-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Haiting Wang ,  Shesh Mani Pandey ,  Jiehui Shu ,  Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Guowei Xu ,  Zhaoying Hu

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

    Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.

    Methods of forming source/drain regions on FinFET devices
    17.
    发明授权
    Methods of forming source/drain regions on FinFET devices 有权

    公开(公告)号：US10347748B2

    公开(公告)日：2019-07-09

    申请号：US15092168

    申请日：2016-04-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Shesh Mani Pandey ,  Muhammad Rahman ,  Srikanth Balaji Samavedam

    IPC: H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L29/08 ,  H01L29/78

    Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity includes an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity.

    NOVEL STI PROCESS FOR SDB DEVICES
    18.
    发明申请
    NOVEL STI PROCESS FOR SDB DEVICES 审中-公开

    公开(公告)号：US20170373144A1

    公开(公告)日：2017-12-28

    申请号：US15195988

    申请日：2016-06-28

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Shesh Mani Pandey

    IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/417

    CPC classification number: H01L29/0653 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66545

    Abstract: A shallow trench isolation (STI) structure is formed having a conventional STI trench structure formed of dielectric material extending into the substrate. A planarizing stack of nitride and oxide is formed above the STI trench structure (and optionally a dummy gate may be formed above this stack). After further conventional processing, the nitride layer results in a structure that extends laterally outward beyond the outer edges of the underlying STI structure—creating a shadow or umbrella structure. The S/D cavity is formed (between the active gate and dummy gate) and the epitaxial S/D regions are grown. The placement and configuration of the nitride layer assists in reducing the amount of substrate material removed adjacent the STI structure during the S/D region cavity formation.

    Fabricating fin-type field effect transistor with punch-through stop region
    20.
    发明授权
    Fabricating fin-type field effect transistor with punch-through stop region 有权
    制造具有穿通停止区域的鳍式场效应晶体管

    公开(公告)号：US09087860B1

    公开(公告)日：2015-07-21

    申请号：US14264179

    申请日：2014-04-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Edmund Kenneth Banghart ,  Yanxiang Liu ,  Shesh Mani Pandey

    IPC: H01L29/76 ,  H01L29/66 ,  H01L27/085 ,  H01L21/76 ,  H01L29/06 ,  H01L29/167 ,  H01L21/265 ,  H01L29/10

    CPC classification number: H01L29/66803 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0638 ,  H01L29/1083 ,  H01L29/167

    Abstract: Methods are provided for fabricating a fin-type field effect transistor(s), having a channel region within a fin. The methods include: establishing a protective material above an upper surface of the fin, and an isolation material adjacent to at least one sidewall of the fin, the isolation material being recessed down from the upper surface of the fin, for instance, for approximately a height of the channel region within the fin; and providing a punch-through stop dopant region within the fin below the channel region, the providing including implanting a punch-through stop dopant into the isolation material and laterally diffusing the punch-through stop dopant from the isolation material into the fin to form the punch-through stop region within the fin beneath the channel region.

    Abstract translation: 提供了用于制造翅片式场效应晶体管的方法，其具有鳍内的沟道区。 所述方法包括：在翅片的上表面上方建立保护材料，以及邻近翅片的至少一个侧壁的隔离材料，隔离材料从翅片的上表面向下凹下，例如约 翅片内的通道区域的高度; 以及在通道区域下方的翅片内提供穿通止动掺杂剂区域，所述提供包括将穿通阻止掺杂剂注入到隔离材料中并将穿通阻止掺杂剂横向扩散到隔离材料进入翅片以形成 在通道区域下方的翅片内的穿通停止区域。

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