公开(公告)号：US09660040B2

公开(公告)日：2017-05-23

申请号：US14926657

申请日：2015-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L29/94 ,  H01L29/417 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

公开(公告)号：US09502528B2

公开(公告)日：2016-11-22

申请号：US14469014

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Mark A. Zaleski ,  Andy Chih-Hung Wei

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653

Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).

Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成第一块掩模。 该第一块掩模覆盖至少一个源/漏（s / d）接触位置的至少一部分。 在未被第一块掩模覆盖的s / d接触位置上形成s / d覆盖层。 该s / d封盖层由第一封盖物质构成。 然后，在半导体结构上形成第二块掩模。 该第二块掩模暴露至少一个门位置。 包括第二封盖物质的栅极覆盖层从暴露的栅极位置移除。 然后沉积金属接触层，其形成与s / d接触位置和栅极接触位置的接触。

公开(公告)号：US09202751B2

公开(公告)日：2015-12-01

申请号：US14246476

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L21/338 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

Abstract translation: 本发明的实施例提供一种改进的半导体结构和制造方法，其提供在两维中自对准的晶体管接触。 使用两个不同的封盖层，每个覆盖层由不同的材料组成。 两个封盖层可以相互选择性地蚀刻。 一个覆盖层用于栅极覆盖，而另一个覆盖层用于源极/漏极覆盖。 选择性蚀刻工艺打开所需的栅极和源极/漏极，而块掩模用于覆盖不是连接方案一部分的元件。 沉积金属化线（层），与开放元件接触以提供它们之间的电连接。

公开(公告)号：US10181522B2

公开(公告)日：2019-01-15

申请号：US15437846

申请日：2017-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tuhin Guha Neogi ,  Scott D. Luning ,  David Pritchard ,  Kasun Anupama Punchihewa

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238

Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.

公开(公告)号：US20180182674A1

公开(公告)日：2018-06-28

申请号：US15905621

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： David C. Pritchard ,  Tuhin Guha Neogi ,  Scott Luning ,  David Doman

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/027 ,  H01L21/321 ,  H01L21/311

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823418 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/14636 ,  H01L29/0847 ,  H01L29/66568

Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.

公开(公告)号：US09947590B1

公开(公告)日：2018-04-17

申请号：US15294228

申请日：2016-10-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： David C. Pritchard ,  Tuhin Guha Neogi ,  Scott Luning ,  David Doman

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/321 ,  H01L21/311 ,  H01L21/027 ,  H01L23/528 ,  H01L23/522 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823418 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/14636 ,  H01L29/0847 ,  H01L29/66568

Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.

公开(公告)号：US20170263715A1

公开(公告)日：2017-09-14

申请号：US15067540

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Sudharshanan Raghunathan ,  Andy Chi-Hung Wei ,  Jason Eugene Stephens ,  Vikrant Kumar Chauhan ,  David Michael Permana

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/49 ,  H01L21/311

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0273 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.

公开(公告)号：US09472455B2

公开(公告)日：2016-10-18

申请号：US14246197

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason E. Stephens ,  Lei Yuan ,  Lixia Lei ,  David Pritchard ,  Tuhin Guha Neogi

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207

Abstract: A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more transistors. The fabricating includes: patterning a first line segment with a first side projection using a first mask; and patterning a second line segment with a second side projection using a second mask. The second line segment is offset from the first line segment, and the patterned second side projection overlies the patterned first side projection, and facilitates defining a cross-stitch segment connecting the first and second line segments. The method further includes selectively cutting the first and second line segments in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment.

Abstract translation: 提供了一种用于在晶片上制造交叉耦合线段以用于例如制造两个或多个晶体管的交叉耦合栅极的方法。 该制造包括：使用第一掩模使具有第一侧面突起的第一线段图案化; 以及使用第二掩模用第二侧面突起构图第二线段。 第二线段与第一线段偏移，并且图案化的第二侧突起覆盖图案化的第一侧突起，并且有助于限定连接第一和第二线段的十字绣线段。 该方法还包括在限定来自第一和第二线段和十字绣段的交叉耦合线段时选择性地切割第一和第二线段。

公开(公告)号：US10068806B2

公开(公告)日：2018-09-04

申请号：US15905621

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： David C. Pritchard ,  Tuhin Guha Neogi ,  Scott Luning ,  David Doman

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L27/146

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823418 ,  H01L23/522 ,  H01L23/5221 ,  H01L23/5222 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/14636 ,  H01L29/0847 ,  H01L29/66568

Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.

公开(公告)号：US20180240885A1

公开(公告)日：2018-08-23

申请号：US15437846

申请日：2017-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tuhin Guha Neogi ,  Scott D. Luning ,  David Pritchard ,  Kasun Anupama Punchihewa

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/665 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823475 ,  H01L21/823835 ,  H01L21/823864 ,  H01L21/823885 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827

Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.