公开(公告)号：US09087881B2

公开(公告)日：2015-07-21

申请号：US13785934

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean X. Lin ,  Xunyuan Zhang ,  Ming He ,  Larry Zhao ,  John Iacoponi ,  Kunaljeet Tanwar

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76847 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.

Abstract translation: 在半导体衬底上形成的层间电介质中的沟槽由底部和侧壁限定。 铜屏障通过屏障上的铜生长促进衬里将沟槽排列。 沟槽有大量铜填充，并且在铜中包括空隙。 具有空隙的铜被除去，包括从侧壁，在底部留下无空隙的铜部分。 浸没在无电解铜浴中促进铜在无空隙铜部分顶部的向上生长，而不会向内侧壁铜生长，导致沟槽的无空隙铜填充。

公开(公告)号：US20140361435A1

公开(公告)日：2014-12-11

申请号：US14470213

申请日：2014-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中形成阻挡层，在阻挡层上形成铜基种子层，将至少一部分铜基 种子层形成铜基氮化物层，在铜基氮化物层上沉积大块铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺，以去除位于沟槽之外的多余材料 / via，从而限定铜基导电结构。 本文公开的装置包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和层之间的铜基硅或氮化锗层 的绝缘材料。

公开(公告)号：US20140145332A1

公开(公告)日：2014-05-29

申请号：US13684871

申请日：2012-11-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Errol T. Ryan ,  Zoran Krivokapic ,  Xunyuan Zhang ,  Christian Witt ,  Ming He ,  Larry Zhao

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a graphene liner layer in at least the trench/via, forming a copper-based seed layer on the graphene liner layer, depositing a bulk copper-based material on the copper-based seed layer so as to overfill the trench/via, and performing at least one chemical mechanical polishing process to remove at least excess amounts of the bulk copper-based material and the copper-based seed layer positioned outside of the trench/via to thereby define a copper-based conductive structure with a graphene liner layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在至少沟槽/通孔中形成石墨烯衬里层，在石墨烯衬层上形成铜基晶种层，沉积大量基于铜的 在铜基种子层上的材料，以便过度填充沟槽/通孔，并进行至少一种化学机械抛光工艺以去除至少过量的大量铜基材料和位于外部的铜基种子层 沟槽/通孔，从而限定铜基导电结构，其中石墨烯衬里层位于铜基导电结构和绝缘材料层之间。

公开(公告)号：US20160379881A1

公开(公告)日：2016-12-29

申请号：US14751380

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ming He ,  Seowoo Nam ,  Yann Mignot ,  Jim Kelly ,  Raghuveer Patlotta ,  Theodorus Standaert

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/528

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect in a first interlayer dielectric. A first cap is formed overlying the first interlayer dielectric adjacent to the interconnect, and a second interlayer dielectric is formed overlying the first interlayer dielectric, the interconnect, and the cap. A contact is formed through the second interlayer dielectric, where the contact includes an overlap region and a connection region. The overlap region directly overlies the first interlayer dielectric adjacent to the interconnect, and the connection region directly contacts the interconnect. The first cap is positioned between the overlap region and the first interlayer dielectric.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在第一层间电介质中形成互连。 第一盖形成在与互连件相邻的第一层间电介质上，并且形成覆盖第一层间电介质，互连和盖的第二层间电介质。 通过第二层间电介质形成触点，其中触点包括重叠区域和连接区域。 重叠区域直接覆盖与互连件相邻的第一层间电介质，并且连接区域直接接触互连。 第一盖位于重叠区域和第一层间电介质之间。

公开(公告)号：US20150087149A1

公开(公告)日：2015-03-26

申请号：US14037774

申请日：2013-09-26

Applicant: Globalfoundries, Inc.

Inventor： Ming He ,  Seowoo Nam ,  Craig Child

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a mask overlying a material to be etched by forming first hard mask segments overlying the material to be etched, forming sacrificial mandrels overlying the material to be etched and around each hard mask segment, forming second hard mask segments overlying the semiconductor substrate and adjacent each sacrificial mandrel, and removing the sacrificial mandrels to form first gaps surrounding each first hard mask segment, wherein each first gap is bounded by a respective first hard mask segment and an adjacent second hard mask segment. The method includes etching the material to be etched through the mask.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括：通过形成覆盖待蚀刻材料的第一硬掩模段形成覆盖待蚀刻材料的掩模，形成覆盖待蚀刻材料和围绕每个硬掩模段的牺牲心轴， 形成覆盖所述半导体衬底并邻近所述牺牲心轴的第二硬掩模段，以及去除所述牺牲心轴以形成围绕每个第一硬掩模段的第一间隙，其中每个第一间隙由相应的第一硬掩模段和相邻的第二硬掩模 分割。 该方法包括通过掩模蚀刻待蚀刻的材料。

公开(公告)号：US08753975B1

公开(公告)日：2014-06-17

申请号：US13757288

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L21/4763

CPC classification number: H01L21/76873 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a trench/via in a layer of insulating material, forming a first layer comprised of silicon or germanium on the insulating material in the trench/via, forming a copper-based seed layer on the first layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based nitride layer positioned between the copper-based conductive structure and the layer of insulating material, wherein the copper-based nitride layer contacts both of the copper-based conductive structure and the layer of insulating material.

Abstract translation: 一种方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中的绝缘材料上形成由硅或锗构成的第一层，在第一层上形成铜基种子层，至少转化为 铜基种子层的一部分成为铜基氮化物层，在铜基氮化物层上沉积大量铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺以除去过量的 位于沟槽/通孔外部的材料，从而限定铜基导电结构。 一种器件包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和绝缘材料层之间的铜基氮化物层，其中 铜基氮化物层接触铜基导电结构和绝缘材料层。

公开(公告)号：US10510675B2

公开(公告)日：2019-12-17

申请号：US15888366

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Somnath Ghosh ,  Eswar Ramanathan ,  Qanit Takmeel ,  Ming He ,  Jeric Sarad ,  Ashwini Chandrashekar ,  Colin Bombardier ,  Anbu Selvam KM Mahalingam ,  Keith P. Donegan ,  Prakash Periasamy

IPC: H01L21/00 ,  H01L23/544 ,  G01N21/552 ,  G01B11/27 ,  H01L21/68

Abstract: Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.

公开(公告)号：US09431294B2

公开(公告)日：2016-08-30

申请号：US14525796

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ming He ,  Errol Todd Ryan ,  Roderick Alan Augur ,  Craig Child ,  Larry Zhao

IPC: H01L21/4763 ,  H01L21/76 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在电介质层中形成互连沟槽，以及形成覆盖在介电层上和互连沟槽内的共形阻挡层。 通过从互连沟槽底部去除共形阻挡层而形成阻挡间隔物，并且在形成阻挡间隔物之后在互连沟槽内形成互连。 在邻近阻挡间隔物的电介质层中形成气隙沟槽，并且顶盖形成在互连和气隙沟槽上方，顶盖与气隙沟槽连接，以在气隙沟槽中产生气隙 。

公开(公告)号：US09318437B1

公开(公告)日：2016-04-19

申请号：US14611740

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming He ,  Kunaljeet Tanwar

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/321 ,  H01L23/00

CPC classification number: H01L23/53238 ,  H01L21/3105 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/26 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a thinner barrier/liner stack for vias and metal lines and the resulting device are disclosed. Embodiments include forming a via through an interlayer dielectric (ILD) and capping layer, down to a first metal layer; forming a moisture scavenging layer precursor over the ILD and on side and bottom surfaces of the via; annealing the moisture scavenging layer precursor, forming a moisture scavenging layer; forming a barrier/liner stack over the moisture scavenging layer; and depositing a second metal layer over the barrier/liner stack and filling the via and trench.

Abstract translation: 公开了形成用于通孔和金属线的较薄阻挡层/衬垫叠层的方法以及所得到的器件。 实施例包括通过层间电介质（ILD）和覆盖层形成通孔，向下到第一金属层; 在ILD上和通孔的侧表面和底表面上形成除湿层前体; 退火除湿层前体，形成除湿层; 在水分清除层上形成阻挡层/衬垫层; 以及在所述阻挡层/衬垫叠层上沉积第二金属层并填充所述通孔和沟槽。

公开(公告)号：US09054052B2

公开(公告)日：2015-06-09

申请号：US13903802

申请日：2013-05-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent Licausi ,  Errol Todd Ryan ,  Ming He ,  Moosung M. Chae ,  Kunaljeet Tanwar ,  Larry Zhao ,  Christian Witt ,  Ailian Zhao ,  Sean X. Lin ,  Xunyuan Zhang

IPC: H01L21/314 ,  H01L21/308 ,  H01L21/32 ,  H01L29/06

CPC classification number: H01L21/314 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L29/06 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

Abstract translation: 提供了一种在制造期间减少对超低k层的损伤的方法的方法。 一方面，一种方法包括：提供含有填充有孔填充材料的孔的固化的超低k膜; 以及改变超低k膜的暴露表面以在超低k膜中提供改性层。 在另一方面，提供一种在超低k膜的表面上包含改性层的半导体器件。