公开(公告)号：US20190237356A1

公开(公告)日：2019-08-01

申请号：US15882465

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ravi Prakash Srivastava ,  Sunil K. Singh

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/0276 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295

Abstract: Interconnect structures and methods for forming an interconnect structure. A dielectric layer of a metallization level is deposited and a trench is patterned in the dielectric layer. A sacrificial layer is formed in the trench in the dielectric layer. The sacrificial layer is patterned to form a first trench and a second trench separated from the first trench by a section of the sacrificial layer. A first metal interconnect is formed in the first trench, a second metal interconnect is formed in the second trench, and a porous cap layer is formed over the first metal interconnect, the second metal interconnect, and the section of the sacrificial layer. After forming the porous cap layer, the section of the sacrificial layer is removed.

公开(公告)号：US10312188B1

公开(公告)日：2019-06-04

申请号：US15867894

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravi P. Srivastava ,  Sunil K. Singh

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit (IC) structure including an interconnect structure is disclosed. The interconnect structure may include a first etch stop layer (ESL) positioned between an initial via layer and a first metal layer of the interconnect structure. The ESL may be positioned adjacent to and surround a metal wire in the first metal layer. A method of forming an interconnect structure is also disclosed. The method may include forming an opening in a first dielectric layer above a substrate; forming a sacrificial semiconductor material in the opening; forming an ESL on the first dielectric layer and sacrificial semiconductor material; forming a second dielectric layer on the ESL; forming an opening in the second dielectric layer to expose a portion of the ESL; removing the exposed portion of the ESL; removing the sacrificial semiconductor material; and forming a conductive material in the openings to form an interconnect structure.

公开(公告)号：US20180299765A1

公开(公告)日：2018-10-18

申请号：US15485498

申请日：2017-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： SherJang Singh ,  Sunil K. Singh ,  Sohan S. Mehta

IPC: G03F1/24 ,  C23C16/02 ,  G03F1/54 ,  G03F1/52 ,  G03F1/46 ,  G03F1/80 ,  G03F1/60

Abstract: A reflective mask with an embedded absorber pattern is provided. The reflective mask may include a low thermal expansion material (LTEM) substrate. A pair of reflective stacks may be included, each reflective stack having a first respective top surface extending from the LTEM substrate to a first extent. A fill stack is between the pair of reflective stacks, the fill stack having a second top surface extending from the LTEM substrate to a second extent, the second extent being below the first extent of the pair of reflective stacks. An extended portion of each of the pair of reflective stacks is above the fill stack thereby forming a recess well between the pair of reflective stacks, the recess well having substantially vertical walls separated by the second top surface of the fill stack. An absorber layer lining the recess well.

公开(公告)号：US10353288B2

公开(公告)日：2019-07-16

申请号：US15824293

申请日：2017-11-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vineet Sharma ,  Sohan S. Mehta ,  Craig D. Higgins ,  Sunil K. Singh ,  Feng Wang

IPC: G03B27/42 ,  G03F7/26 ,  G03F7/00 ,  G03F7/38

Abstract: A litho-litho-etch double patterning method including forming a resist layer by coating a substrate with a resist composition; exposing the resist layer to a first radiant energy density of UV rays; forming a first pattern in the resist layer by developing the resist layer with a positive developer; exposing the resist layer to a second radiant energy density of UV rays; and forming a second pattern in the resist layer by developing the resist layer with a negative developer, the second pattern including one or more features of the first pattern.

公开(公告)号：US20190163054A1

公开(公告)日：2019-05-30

申请号：US15824293

申请日：2017-11-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vineet Sharma ,  Sohan S. Mehta ,  Craig D. Higgins ,  Sunil K. Singh ,  Feng Wang

IPC: G03F7/00 ,  G03F7/38

CPC classification number: G03F7/0035 ,  G03F7/38

Abstract: A litho-litho-etch double patterning method including forming a resist layer by coating a substrate with a resist composition; exposing the resist layer to a first radiant energy density of UV rays; forming a first pattern in the resist layer by developing the resist layer with a positive developer; exposing the resist layer to a second radiant energy density of UV rays; and forming a second pattern in the resist layer by developing the resist layer with a negative developer, the second pattern including one or more features of the first pattern.

公开(公告)号：US20190108942A1

公开(公告)日：2019-04-11

申请号：US15729992

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Jagar Singh

IPC: H01F41/063 ,  H01F41/12 ,  H01F41/34 ,  H01F5/00 ,  H01F5/06

Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.

公开(公告)号：US10177029B1

公开(公告)日：2019-01-08

申请号：US15790249

申请日：2017-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Sunil K. Singh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Interconnect structures and methods for forming an interconnect structure. A sacrificial layer is formed on a substrate and an interconnect opening is formed that extends vertically through the sacrificial layer into the substrate. The interconnect opening is filled with a conductor to form a conductive feature. After filling the interconnect opening with the conductor, a dielectric layer is formed on the sacrificial layer. After the dielectric layer is formed on the sacrificial layer, the sacrificial layer is removed to form an air gap layer arranged vertically between the dielectric layer and the substrate.

公开(公告)号：US20180158723A1

公开(公告)日：2018-06-07

申请号：US15370585

申请日：2016-12-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ravi Srivastava ,  Sunil K. Singh

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  G03F7/09 ,  G03F7/039 ,  G03F7/038 ,  G03F7/20 ,  G03F7/26 ,  G03F7/16

CPC classification number: H01L21/76816 ,  G03F7/0043 ,  G03F7/094 ,  G03F7/095 ,  G03F7/40 ,  H01L21/0274 ,  H01L21/0337

Abstract: Methods of lithographic patterning a dielectric layer. A first resist layer is formed on a hardmask layer, and a second resist layer is formed on the first resist layer. The second resist layer is patterned to form a first opening, which is transferred from the second resist layer to the first resist layer. The second resist layer is removed from the first resist layer after the first opening is transferred from the second resist layer to the first resist layer. The first resist layer is patterned to form a second opening laterally displaced in the first resist layer from the first opening. The first resist layer is comprised of a metal oxide photoresist that is removable selective to the hardmask layer. The hardmask layer and the dielectric layer may be subsequently patterned using first resist layer.

公开(公告)号：US20170025347A1

公开(公告)日：2017-01-26

申请号：US15043011

申请日：2016-02-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Mark A. Zaleski ,  Akshey Sehgal

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

Abstract translation: 本发明的实施例提供了一种用于BEOL（后端）集成的半导体结构。 定向自组装（DSA）材料被沉积并退火以形成两个不同的相位区域。 选择性地去除一个相区，并且剩余的相区用作在金属和/或电介质的下层中形成空腔的掩模。 然后重复该过程以形成具有由电介质区域分离的金属图案的复杂结构。

公开(公告)号：US10832842B2

公开(公告)日：2020-11-10

申请号：US16550431

申请日：2019-08-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Jagar Singh

IPC: H01F5/06 ,  H01F5/00 ,  H01F17/00 ,  H01L49/02

Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.